MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 718

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Scan Chain Test Access Port
8.4 INSTRUCTION REGISTER
The QUICC JTAG implementation includes the public instructions (EXTEST, SAMPLE/
PRELOAD, and BYPASS), and also supports the CLAMP instruction. One additional public
instruction (HI-Z) provides the capability for disabling all device output drivers. The QUICC
includes a 3-bit instruction register without parity consisting of a shift register with three par-
allel outputs. Data is transferred from the shift register to the parallel outputs during the
update-IR controller state. The three bits are used to decode the five unique instructions
listed in Table 8-3.
The parallel output of the instruction register is reset to all ones in the test-logic-reset con-
troller state. Note that this preset state is equivalent to the BYPASS instruction.
During the capture-IR controller state, the parallel inputs to the instruction shift register are
loaded with the CLAMP command code.
8.4.1 EXTEST
The external test (EXTEST) instruction selects the 196-bit boundary scan register. EXTEST
also asserts internal reset for the QUICC system logic to force a predictable benign internal
state while performing external boundary scan operations.
By using the TAP, the register is capable of a) scanning user-defined values into the output
buffers, b) capturing values presented to input pins, c) controlling the direction of bidirec-
tional pins, and d) controlling the output drive of three-stateable output pins. For more details
on the function and use of EXTEST, refer to the scan chaindocument.
8.4.2 SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction initializes the boundary scan register output cells prior
to selection of EXTEST. This initialization ensures that known data will appear on the out-
puts when entering the EXTEST instruction. The SAMPLE/PRELOAD instruction also pro-
vides a means to obtain a snapshot of system data and control signals. In the case of the
QUICC, this functionality is not supported.
8-10
Since there is no internal synchronization between the scan
chain clock (TCK) and the system clock (CLKO1), the user must
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 8-3. Instruction Decoding
B2
0
0
X
1
1
MC68360 USER’S MANUAL
Code
Go to: www.freescale.com
B1
0
0
1
0
0
B0
NOTE
X
0
1
0
1
CLAMP and BYPASS
SAMPLE/PRELOAD
Instruction
BYPASS
EXTEST
HI-Z