MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 523

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.10.19.4.1 GSMR Programming. The GSMR programming sequence is as follows:
1. The MODE bits should be set to AppleTalk.
2. The ENT and ENR bits should be set.
3. The DIG bits should be set for normal operation, with the CD and CTS pins
4. The RDCR and TDCR bits should usually be set to 16x clock.
5. The TENC and RENC bits should be set for FM0.
6. The Tend bit should be zero.
7. The TPP bits should be 11.
8. The TPL bits should be set to 000 to transmit the next frame with no
9. The TINV and RINV bits should be zero.
10. The TSNC bits should be set to 1.5 bit times 10.
11. The EDGE bits should be zero.
12. RTSM should be zero.
13. All other bits should be set to zero or to their default condition.
RTS
TXD
grounded or with the CD and CTS pins configured for parallel I/O, which causes
CD and CTS to be internally asserted to the SCC.
synchronization sequence and to 001 to transmit the next frame with
the LocalTalk synchronization sequence. For example, data frames do
not require a preceding synchronization sequence. These bits may be
modified on the fly if the AppleTalk protocol is selected.
SYNC
6-BIT
SEQ
STANDARD HDLC FRAME HANDLING
FLAGS
HDLC
TWO
Figure 7-62. Connecting the QUICC to LocalTalk
ADDR.
DEST.
Freescale Semiconductor, Inc.
QUICC
SCC
For More Information On This Product,
SOURCE
ADDR.
RXD
TXD
RTS
CONTROL
MC68360 USER’S MANUAL
Go to: www.freescale.com
BYTE
STORED IN TRANSMIT BUFFER
STORED IN RECEIVE BUFFER
TX ENABLE
Tx DATA
Rx DATA
RS-422
DATA
Serial Communication Controllers (SCCs)
MINI-DIN 8
CRC-16
CLOSING
FLAG
16 ONES
(ABORT)