MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 505

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

E—Empty
Bits 14, 8, 6—Reserved
W—Wrap (Final BD in Table)
I—Interrupt
L—Last in Frame
F—First in Frame
This bit is set by the HDLC controller when this buffer is the last in a frame. This implies
the reception of a closing flag or reception of an error, in which case one or more of the
CD, OV, AB, and LG bits are set. The HDLC controller will write the number of frame oc-
tets to the data length field.
This bit is set by the HDLC controller when this buffer is the first in a frame.
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE: Entries in boldface must be initialized by the user.
0 = The data buffer associated with this BD has been filled with received data, or data
1 = The data buffer associated with this BD is empty, or reception is currently in
0 = This is not the last buffer descriptor in the Rx BD table.
1 = This is the last buffer descriptor in the Rx BD table. After this buffer has been used,
0 = The RXB bit is not set after this buffer has been used, but RXF operation remains
1 = The RXB or RXF bit in the HDLC event register will be set when this buffer has
0 = This buffer is not the last in a frame.
1 = This buffer is the last in a frame.
0 = The buffer is not the first in a frame.
1 = The buffer is the first in a frame.
reception has been aborted due to an error condition. The CPU32+ core is free to
examine or write to any fields of this Rx BD. The CP will not use this BD again while
the E-bit remains zero.
progress. This Rx BD and its associated receive buffer are owned by the CP. Once
the E-bit is set, the CPU32+ core should not write any fields of this Rx BD.
the CP will receive incoming data into the first BD in the table (the BD pointed to
by RBASE). The number of Rx BD s in this table is programmable, and is deter-
mined only by the W-bit and the overall space constraints of the dual-port RAM.
unaffected.
been used by the HDLC controller. These two bits may cause interrupts (if en-
abled).
15
E
14
—
13
Freescale Semiconductor, Inc.
W
For More Information On This Product,
12
I
MC68360 USER’S MANUAL
Go to: www.freescale.com
11
L
10
F
CM
RX DATA BUFFER POINTER
9
DATA LENGTH
—
8
DE
Serial Communication Controllers (SCCs)
7
—
6
LG
5
NO
4
AB
3
CR
2
OV
1
CD
0