MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 928

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

RISC Microcode from RAM
C.4 ASYNCHRONOUS HDLC FOR PPP
Asynchronous HDLC is a frame-based protocol (see Figure 3), defined by the Internet Engi-
neering Task Force (IETF) "Request For Comments #1549" which uses HDLC framing tech-
niques in conjunction with UART-type characters. This protocol is typically used as the
physical layer for the Point-to-Point (PPP) protocol. While this protocol can be implemented
by the UART controller on the QUICC in conjunction with the CPU32+, it is more efficient
and less compute-intensive for the CPU to allow the Communications Processor Module
(CPM) of the QUICC to perform the framing and transparency functions of the protocol.
C.4.1 Key Features
C-6
• Flexible data buffer structure which allows an entire frame or a section of a frame to be
• Separate interrupts for received frames and transmitted buffers.
• Automatic 16-bit CRC generation and checking (CRC-CCITT).
• Automatic generation of opening and closing flags.
1 x 10 Mbit/s non-scrambling
1 x 6 Mbit/s with scrambling
2 x 2 Mbit/s with scrambling
2 x 2 Mbit/s non-scrambling
transmitted and received.
ATOM1 Channels
Ethernet
Figure C-3. Asynchronous HDLC Block Diagram
MC68160
Interface
Interface
EEST
WAN
WAN
Freescale Semiconductor, Inc.
For More Information On This Product,
Consumed (est)
Risc Bandwidth
Table C-3. ATOM1 Configuration
90%
90%
40%
40%
MC68360 USER’S MANUAL
Go to: www.freescale.com
SCC3
SCC1
SCC2
MC68360
QUICC
3 x 64Kbit HDLC or Transparent
2 x 64Kbit HDLC or Transparent
2 x 2.5 Mbit HDLC or Transparent, 9.6 Kbit SMC UART
1 x 10 Mbit Ethernet, 9.6 Kbit SMC UART
SCC4
Possible Configuration of Other Channels
RS232
Driver
Asynchronous
HDLC
Modem