MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 715

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

$=These pins are implemented differently in normal mode and in JTAG mode—open drain in normal mode, TS-
O in JTAG mode.
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
DATA FROM
SYSTEM
IO.ctl
IO.ctl
IO.ctl
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LOGIC
1—EXTEST / CLAMP
0—OTHERWISE
pchh.ctl
pblh.ctl
pchl.ctl
pc11
pc10
pb8
pb7
pb6
pb5
pb4
pb3
pb2
pb1
pb0
pc9
pc8
pc7
pc6
pc5
Freescale Semiconductor, Inc.
Table 8-2. Boundary Scan Bit Definition
G1
Figure 8-3. Output Latch Cell (O.Latch)
1
1
For More Information On This Product,
MUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
MC68360 USER’S MANUAL
Go to: www.freescale.com
FROM
LAST
CELL
pchh.ctl
pchh.ctl
pchh.ctl
pchh.ctl
pbhl.ctl
pbhl.ctl
pblh.ctl
pblh.ctl
pblh.ctl
pblh.ctl
pblh.ctl
pblh.ctl
pblh.ctl
pchl.ctl
pchl.ctl
pchl.ctl
SHIFT DR
—
—
—
G1
1
1
MUX
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
CLOCK DR
Output
IO.ctl
IO.ctl
IO.ctl
IO.ctl
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D
C
Scan Chain Test Access Port
pclh.ctl
Resets
g12.ctl
g13.ctl
g14.ctl
TO NEXT
Avec
Rmc
Berr
Perr
Irq2
Irq3
Irq5
Irq1
Halt
pc4
pc3
pc2
pc1
pc0
UPDATE DR
CELL
TO OUTPUT
BUFFER
D
C
TS-O
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
$
$
$
$
pchl.ctl
pclh.ctl
pclh.ctl
pclh.ctl
pclh.ctl
g12.ctl
g12.ctl
g13.ctl
g13.ctl
g14.ctl
g14.ctl
g14.ctl
—
—
—
—
—
—
—