MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 255

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

This gives a range from 62.5 ms, with a PITR value of $01, to 15.94 s, with a PITR value of
$FF.
For a fast calculation of PIT period using a 32.768-kHz crystal, the following equations can
be used:
With prescaler disabled:
PIT period = PITR (122 s)
With prescaler enabled:
PIT period = PITR (62.5 ms)
6.3.2.2 USING THE PIT AS A REAL-TIME CLOCK. The PIT can be used as a real-time
clock interrupt by setting it up to generate an interrupt with a 1-second period. When using
a 32.768-kHz (or 4.192-MHz) crystal, the PITR should be loaded with a value of 16 decimal
($10) with the prescaler enabled to generate interrupts at a 1-sec rate.
6.3.3 Freeze Support
FREEZE is asserted by the CPU32+ if a breakpoint is encountered with background mode
enabled. Refer to Section 5 CPU32+ for more information on the background mode. When
FREEZE is asserted, the double bus fault monitor and spurious interrupt monitor continue
to operate normally. However, the SWT, the bus monitor, and the PIT may be affected. Set-
ting the FRZ1 bit in the MCR disables the SWT and the PIT when FREEZE is asserted. Set-
ting the FRZ0 bit in the MCR disables the bus monitor when FREEZE is asserted.
If the CONFIG pins are configured with the CPU32+ core enabled, then one clock after reset
is complete, the CONFIG2 pin will become the FREEZE output. Thus, the pin will start driv-
ing low one clock after reset. It will then be asserted (high) if the freeze condition occurs. If
the CONFIG pins configure the QUICC to slave mode, then the FREEZE output is not avail-
able.
6.3.4 Low-Power Stop Support
Executing the LPSTOP instruction provides reduced power consumption when the QUICC
is idle, with only the SIM remaining active. Operation of the SIM60 is controlled by the
PLLCR. LPSTOP disables the clock to the SWT in the low state. The SWT, which remains
stopped until the LPSTOP mode is ended, begins to run again on the next rising clock edge.
When the CPU32+ executes the STOP instruction (as opposed
to LPSTOP), the SWT continues to run. If the SWT is enabled,
it issues a reset or interrupt when its timeout occurs.
Freescale Semiconductor, Inc.
PIT period
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
=
NOTE
PITR count value
16
System Integration Module (SIM60)