MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 686

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Parallel I/O Ports
7.14.6 Port B Pin Functions
Refer to Table 7-20 for the description of all port B pin options. All port B pins except PB17
and PB16 may be open-drain. Port B pins are independently configured as a general-pur-
pose I/O pins if the corresponding bit in the port B pin assignment register (PBPAR) is
cleared. They are configured as dedicated on-chip peripheral pins if the corresponding
PBPAR bit is set.
When acting as a general-purpose I/O pin, the signal direction for that pin is determined by
the corresponding control bit in the port B data direction register (PBDIR). The port I/O pin
is configured as an input if the corresponding PBDIR bit is cleared; it is configured as an out-
put if the corresponding PBDIR bit is set. All PBPAR bits and PBDIR bits are cleared on total
system reset, configuring all port B pins as general-purpose input pins.
If a port B pin is selected as a general-purpose I/O pin, it may be accessed through the port
B data register (PBDAT). Data written to the PBDAT is stored in an output latch. If a port B
pin is configured as an output, the output latch data is gated onto the port pin. In this case,
when PBDAT is read, the port pin itself is read. If a port B pin is configured as an input, data
written to PBDAT is still stored in the output latch but is prevented from reaching the port
pin. In this case, when PBDAT is read, the state of the port pin is read.
All of the port B pins have more than one option. These options include on-chip peripheral
functions relating to the IDMA, Ethernet CAM interface, SPI, SMC1, SMC2, TDMa, and
TDMb.
Port B is also multiplexed with the PIP. The PIP is a CPM parallel port that can implement
fast parallel interfaces, such as Centronics. For a functional description of the dedicated pin
functions of the PIP, refer to 7.13 Parallel Interface Port (PIP).
PB3–PB5 and PB16 have an unusual property in that their on-chip peripheral functions
(BRGO4, BRGO3, BRGO2, and BRGO1) are repeated in port A. This gives an alternate way
to output the BRGO pins if other functions are used on port A. PB12–PB15 have an unusual
property in that their on-chip peripheral functions (such as RTSx or L1ST1) are repeated in
port C. This gives an alternate location to output these pins if other functions on port C are
used.
7-362
If the user does not use the PIP, the description in this section is
sufficient to describe the features of port B, and the PIP descrip-
tion does not need to be studied.
The PIP STRBI and STRBO pins are not listed in Table 7-20.
See 7.13 Parallel Interface Port (PIP) for instructions on how to
enable them.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES