MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 360

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

IDMA Channels
The IBPTR entry points to the next BD that the IDMA will transfer data to when it is in IDLE
state or points to the current BD during transfer processing. After a reset or when the end of
an IDMA BD table is reached, the CP initializes this pointer to the value programmed in the
IBASE entry.
ISTATE and ITEMP are for RISC use only.
7.6.4.2.2 IDMA Buffer Descriptors (BDs). Source addresses, destination addresses, and
byte counts are presented to the RISC controller using special IDMA BDs. The RISC con-
troller reads the BDs, programs the IDMA channel, and notifies the CPU32+ about the com-
pletion of a buffer transfer using the IDMA BDs. This concept is like that used for the serial
channels on the QUICC, except that the BD is larger to contain additional information.
The following bits are prepared by the user before transfer and are set by the RISC controller
after the buffer has been transferred.
V—Valid
7-36
NOTE: Entries in boldface must be initialized by the user.
OFFSET + C
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
OFFSET + 8
OFFSET + A
OFFSET + E
0 = The data buffers associated with this BD are not currently ready for transfer. The
1 = The data buffers have been prepared for transfer by the user. (Note that only one
user is free to manipulate this BD or its associated data buffer. When it is not in
auto buffer mode, the RISC controller clears this bit after the buffer has been trans-
ferred (or after an error condition is encountered).
data buffer needs to be prepared if the source/destination is a peripheral device.)
It may be only the source data buffer when the destination is a device or the desti-
nation data buffer when the source is a device. No fields of this BD may be written
by the user once this bit is set.
15
V
The only difference between auto buffer mode and buffer chain-
ing mode is that the V-bit is not cleared by the RISC controller in
the auto buffer mode. Auto buffer mode is enabled by the CM bit.
14
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13
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Freescale Semiconductor, Inc.
For More Information On This Product,
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I
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MC68360 USER’S MANUAL
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Go to: www.freescale.com
10
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DESTINATION DATA BUFFER POINTER
SOURCE DATA BUFFER POINTER
NOTE
CM
9
DATA LENGTH
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8
—
7
—
6
—
5
—
4
—
3
SE
2
DE
1
DA
0