MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 941

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

A/D Converters 7-312
A/D Field 5-68
A/D Register 5-70, 5-71
A26–A0 2-1
A31–A28 2-1
Accessing the HDLC Bus 7-192
Achieving Synchronization in Transparent
ACK 7-333
Address
Address Bus 2-1
Address Error Exception 5-42, 5-46
Address Multiplexing 6-58
Address Register 5-6, 5-7
Address Strobe 4-4
ADI B-9
A-Line 5-44, 5-56, 5-59
Alternate Function Code 5-6
AMUX 2-7, 2-9, 6-48, 6-49
AppleTalk 1-10, 7-116, 7-117, 7-170, 7-196
AppleTalk Controller 7-196
AppleTalk Memory Map and Programming
Applications 9-1
Arbitration Level 6-33
Arbitration Synchronous Timing Mode 6-31
Ethernet Address Recognition 7-252
AppleTalk Controller 7-196
AppleTalk Memory Map and
Connecting the QUICC to LocalTalk 7-
GSMR Programming 7-199
HDLC Frames 7-196
LocalTalk 7-196
LocalTalk Frame Format 7-197
PSMR Programming 7-200
QUICC AppleTalk Hardware Connection
Mode 7-223
Model 7-198
Programming Model 7-198
199
7-198
A
Freescale Semiconductor, Inc.
Thi d
For More Information On This Product,
MC68356 USER’S MANUAL
Go to: www.freescale.com
t
INDEX
t d ith F
Architectural Approach 1-6
Architecture Overview 1-4
AS 2-8, 2-13, 4-3, 6-30, 6-63, 7-41, 7-44, 7-
Asynchronous 4-20
Asynchronous Protocols 7-134
ATEMP 5-62, 5-72
Auto Baud 7-166
Auto Buffer 7-34
Auto Buffer Example 7-56
Autovector 4-6, 4-38
AVEC 2-8, 4-6, 4-38, 4-41, 6-8, 6-26, 6-48
AVECO 6-26, 6-48
AVR 6-34
B0 5-49, 5-51, 5-52, 5-53, 5-54, 5-57
B1 5-49, 5-51, 5-53
Background 5-14, 5-26, 5-34
Background Processing State 5-59
Bank Parity 6-62
Base Address 3-1
BCLRI 4-58, 6-25, 6-33
BCLRIID 6-25
BCLRO 2-9, 2-10, 6-25, 6-31, 6-33, 7-44, 7-
BCR 7-31
BDLE 7-204
BDLE-BISYNC DLE Register 7-208
BERR 2-10, 4-5, 4-20, 4-41, 7-51
BERR Signal 5-40
BG 2-9, 2-10, 4-49, 4-53, 6-26, 6-31, 6-32,
BGACK 2-9, 4-49, 6-26, 6-31, 7-44
BGND 5-60, 5-61, 5-62
Bidirectional Centronics 7-331
Big-Endian 7-126, 7-321
BISYNC 7-114, 7-115, 7-200
BISYNC Channel Frame Reception 7-
58
51, 7-58
7-44
M k 4 0 4
202
B