MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 732

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Applications
The memory controller status register (MSTAT) is used for reporting parity errors and does
not require initialization.
The eight base registers (BRs), one for each memory bank, should be configured as follows:
The eight option registers (ORs), one for each memory bank, should be configured as fol-
lows:
9.1.3.3 USING THE QUICC IN 16-BIT DATA BUS MODE. For systems that do not require
a full 32-bit data bus capability, the QUICC offers a 16-bit data bus mode. A system with 16-
bit data bus mode is almost the same as the system shown in this section. Only a few
changes are required.
9-12
NCS should normally be cleared.
DWQ depends on timing. It must be set if page mode is used for the DRAMs.
DW40 is not used and should be cleared.
AMUX should be set.
The BA31–BA11 bits may be set as desired. Different memory arrays should not overlap.
For simplicity, FC3–FC0 can be cleared.
TRLXQ should normally be cleared for memory interfaces.
BACK40 is not used and should be cleared.
CSNT40 is not used and should be cleared.
CSNTQ should normally be cleared.
PAREN should be set for memory banks that use parity.
WP should be set for EPROM, burst EPROM, and flash EPROM; otherwise, it should be
cleared.
V should be set if the memory bank is used.
The TCYC bits should be set to determine the number of wait states required.
The AM27–AM11 bits should be programmed to determine the block size of the chip se-
lect or RASx line. This should be the total number of bytes in each memory array.
FCM3–FCM0 may be set to all zeros to allow the chip select or RASx line to assert on all
function codes except CPU space (interrupt acknowledge). It is advisable to program
FCM3–FCM0 to zeros, at least during the initial stages of debugging.
BCYC1–BCYC0 are not used and should be cleared.
PGME may be set as desired to enable page mode if this is a DRAM bank.
SPS1–SPS0 should be set to 10 for the byte-wide memory banks, such as EPROM, and
cleared for the 32-bit-wide memory banks.
DSSEL should be set only if this is a DRAM bank.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com