MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 701

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The following list gives an example of how to find the beginning of the interrupt handler from
the interrupt vector. SCC1 is used as an example.
7.15.5 CPIC Programming Model
The user interfaces with the CPIC via four registers. The CICR defines the overall CPM
interrupt attributes. The CIPR indicates which CPM interrupt sources require interrupt ser-
vice. The CIMR allows the user to prevent any CPM interrupt source from generating an
interrupt request. The CISR allows a fully nested environment capability for interrupt
requests within the CPM interrupt level.
7.15.5.1 CPM INTERRUPT CONFIGURATION REGISTER (CICR). The 24-bit read-write
CICR defines the request level for the CPM interrupts, the priority between the SCCs, the
highest priority interrupt, and the vector base address. The CICR, which can be dynamically
changed by the user, is cleared at reset.
SCdP—SCCd Priority Order
1. Formulate the 8-bit vector. The three MSBs come from VBA2–VBA0 in the CICR. As-
2. Multiply by 4 to get the offset address of the vector in the vector table. Thus, the offset
3. Determine the full vector address. In a CPU32+ system, the offset is added to the vec-
4. Determine the location of the interrupt handler. At location $800002F8, the address of
These two bits define which SCC will assert its request in the SCCd priority position. The
user should not program the same SCC to more than one priority position (a, b, c, or d).
These bits may be changed dynamically.
00 = SCC1 will assert its request in the SCCd position.
01 = SCC2 will assert its request in the SCCd position.
10 = SCC3 will assert its request in the SCCd position.
11 = SCC4 will assert its request in the SCCd position.
sume these are programmed to 101b. The five LSBs have a fixed value of 11110b (see
Table 7-22). Thus, the 8-bit vector is 10111110b. This is the value presented on the
bus during an interrupt acknowledge cycle.
address is 1011111000b = $2F8.
tor base register in the CPU32+. Assuming that the vector base register = $80000000,
the final vector address is $800002F8.
the interrupt handler is stored. If the long word at location $800002F8 contains
$80001000, then the first instruction of the SCC1 interrupt handler will be found at
$80001000.
IHP3
23
11
SCdP
HP2
22
10
Freescale Semiconductor, Inc.
HP1
21
9
For More Information On This Product,
SCcP
HP0
20
8
MC68360 USER’S MANUAL
Go to: www.freescale.com
VBA2
19
7
SCbP
VBA1
18
6
VBA0
17
5
SCaP
16
4
IRL2
15
3
—
CPM Interrupt Controller (CPIC)
IRL1
14
2
IRL0
13
1
HP4
SPS
12
0