MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 84

IC MPU QUICC 25MHZ 240-FQFP

MC68EN360CAI25L

Manufacturer Part Number
MC68EN360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Series
MC68000r

Specifications of MC68EN360CAI25L

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Core Size
32 Bit
Cpu Speed
25MHz
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
No. Of Pins
240
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EN360CAI25L
Manufacturer:
APLHA
Quantity:
12 000
Part Number:
MC68EN360CAI25L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EN360CAI25L
Manufacturer:
FREESCALE
Quantity:
20 000
Bus Operation
The SIZ0 and SIZ1 outputs indicate the remaining number of bytes to be transferred during
the current bus cycle (see Table 4-3).
The number of bytes transferred during a write or read bus cycle is equal to or less than the
size indicated by the SIZx outputs, depending on port width and operand alignment. For
example, during the first bus cycle of a long-word transfer to a word port, the SIZx outputs
indicate that four bytes are to be transferred, although only two bytes are moved on that bus
cycle.
A0 and A1 also affect operation of the data multiplexer. During an operand transfer, A2-A31
indicate the long-word base address of that portion of the operand to be accessed; A0 and
A1 indicate the byte offset from the base. Table 4-4 lists the encoding of A0 and A1 and the
corresponding byte offset from the long-word base.
4-8
INCREASING
ADDRESSES
MEMORY
MULTIPLEXER
EXTERNAL
REGISTER
DATA BUS
ADDRESS
xxxxxxxx0
xxxxxxxx0
xxxxxxxx0
2
1
2
3
Figure 4-3. QUICC Interface to Various Port Sizes
D31–D24
BYTE 0
BYTE 0
BYTE 2
BYTE 0
BYTE 1
BYTE 2
BYTE 3
0P0
0
Freescale Semiconductor, Inc.
For More Information On This Product,
SIZ1
0
1
1
0
8-BIT PORT
Table 4-3. SIZx Encoding
MC68360 USER’S MANUAL
Go to: www.freescale.com
D23–D16
BYTE 3
BYTE 1
BYTE 1
ROUTING AND DUPLICATION
0P1
1
SIZ0
1
0
1
0
16-BIT PORT
D15–D8
BYTE 2
0P2
2
Byte
Word
3 Bytes
Long Word
Size
BYTE 3
D7–D0
0P3
3
32-BIT PORT
EXTERNAL BUS
INTERNAL TO
THE MC68360

Related parts for MC68EN360CAI25L