MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 474

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
7.10.16.8 UART CONTROL CHARACTERS (RECEIVER). The UART has the capability to
recognize special control characters. These characters may be used when the UART func-
tions in a message-oriented environment. Up to 8 control characters may be defined by the
user in the control characters table. Each character may be either written to the receive
buffer (upon which the buffer is closed and a new receive buffer taken) or rejected. If
rejected, the character is written to the received control character register (RCCR) in internal
RAM, and a maskable interrupt is generated. This method is useful for notifying the user of
the arrival of control characters (e.g., XOFF) that are not part of the received messages.
The UART uses a table of 16-bit entries to support control character recognition. Each entry
consists of the control character, a valid bit, and a reject character bit.
7-150
OFFSET + 10
OFFSET + 12
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + E
MASTER
T
T
1
R
R
Figure 7-47. Two Configurations of UART Multidrop Operation
UADDR1
UADDR2
15
E
E
E
E
1
SLAVE 1
14
R
R
R
R
T
T
1
2
R
R
13
Freescale Semiconductor, Inc.
TWO 8-BIT ADDRESSES
CAN BE AUTOMATICALLY
RECOGNIZED IN EITHER
CONFIGURATION.
For More Information On This Product,
12
SLAVE 2
T
T
MC68360 USER’S MANUAL
3
11
Go to: www.freescale.com
R
R
10
9
SLAVE 3
T
T
4
R
R
8
•
•
•
7
PAODR
R
R
+V
+V
CHARACTER1
CHARACTER2
CHARACTER3
CHARACTER8
CHOOSE WIRED-OR
OPERATION IN THE PORT A
OPEN-DRAIN REGISTER TO
ALLOW MULTIPLE TRANSMIT
PINS TO BE DIRECTLY
CONNECTED.
RCCM
RCCR
0