MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 766

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Applications
future 16M
36 DRAM SIMMs. In fact, this multiplexing scheme allows SIMMs of many dif-
ferent sizes to be used on the board without hardware modification.
This particular SIMM also includes parity support, supported with the PRTY3–PRTY0 sig-
nals.
This design also uses the RAS1 double-drive capability, whereby the RAS1DD signal is out-
put by the QUICC to increase the effective drive capability of the RAS1 signal. The RAS1
line should be programmed to respond to a 4-Mbyte address space.
After power-on reset, the software must wait the required time before accessing the DRAM.
The required eight read cycles must then be performed either in software or by waiting for
the refresh controller to perform these accesses.
9.4.2.9 DRAM DEVICES. Figure 9-16 shows the interface to a standalone DRAM device. In
this case, the MCM54260 256K
16 DRAM device is chosen. This allows a full 32-bit-wide
DRAM solution using only two DRAM devices, with byte writes still supported using the
upper and lower CASx pins. Both the MC68EC040 and the QUICC can access the DRAM
array. The RAS1 line should be programmed to respond to a 1-Mbyte address space.
The address multiplexing scheme is the same as that for the DRAM SIMM. No parity support
is provided in this case. The RAS1DD signal is not used in this case since only two devices
are supported.
After power-on reset, the software must wait the required time before accessing the DRAM
(approximately 100 s). The required eight read cycles must then be performed either in
software or by waiting for the QUICC refresh controller to perform these accesses.
9-46
MC68360 USER’S MANUAL
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