MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 562

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
7.10.23.3 LEARNING ETHERNET ON THE QUICC. The following paragraphs detail the
Ethernet functionality on the QUICC. However, they show the additions made to the stan-
dard SCC functionality to implement Ethernet. Therefore, the reader is encouraged to learn
the basics of the SCCs and the overall architecture of the CPM before attempting to learn
this section in great detail.
A first-time user of the QUICC who plans to use Ethernet on the QUICC should first read the
following sections of this user manual.
7-238
• External CAM Support on Both Serial and System Bus Interfaces
• Up to Eight Parallel I/O Pins May Be Sampled and Appended to Any Frame
• Heartbeat Indication
• Transmitter Network Management and Diagnostics
• Receiver Network Management and Diagnostics
• Error Counters
• Internal and External Loopback Mode
1. 7.1 RISC Controller, 7.2 Command Set, and 7.3 Dual-Port RAM. The RISC controller
2. 7.7 SDMA Channels discusses how SDMA channels are used to transfer data to/from
3. 7.8.9 NMSI Configuration explains how clocks are routed to the SCCs through the
4. 7.10.1 SCC Overview contains more detailed information on the SCCs that are appli-
—Physical—One 48-Bit Address Recognized or 64-Bin Hash Table for Physical Ad-
—Logical—64-Bin Group Address Hash Table plus Broadcast Address Checking
—Promiscuous—Receives All Addresses, but Discards Frame If Reject Pin Asserted
—Lost Carrier Sense
—Underrun
—Number of Collisions Exceeded the Maximum Allowed
—Number of Retries per Frame
—Deferred Frame Indication
—Late Collision
—CRC Error Indication
—Nonoctet Alignment Error
—Frame Too Short
—Frame Too Long
—Overrun
—Busy (Out of Buffers)
—Discarded Frames (Out of Buffers or Overrun Occurred)
—CRC Errors
—Alignment Errors
is used to issue special commands to the Ethernet channel. The dual-port RAM is
used to load Ethernet parameters and initialize BDs for use by the Ethernet channel.
the Ethernet channel and system memory.
bank of clocks.
dresses
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com