MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 586

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
erenced by the channel’s Tx BD table. The Ethernet controller confirms transmission or indi-
cates error conditions using the BDs to inform the host that the buffers have been serviced.
R—Ready
PAD—Short Frame Padding
W—Wrap (Final BD in Table)
I—Interrupt
L—Last
7-262
This bit is valid only when the L-bit is set; otherwise, it is ignored.
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE: Entries in boldface must be initialized by the user.
0 = The data buffer associated with this BD is not ready for transmission. The user is
1 = The data buffer, which has been prepared for transmission by the user, has not
0 = Do not add PADs to short frames.
1 = Add PADs to short frames. Pad bytes will be inserted until the length of the trans-
0 = This is not the last BD in the Tx BD table.
1 = This is the last BD in the Tx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been serviced.
1 = The TXB bit or TXE bit will be set in the Ethernet event register after this buffer has
0 = This is not the last buffer in the transmit frame.
1 = This is the last buffer in the current transmit frame.
free to manipulate this BD or its associated data buffer. The CP clears this bit after
the buffer has been transmitted or after an error condition is encountered.
been transmitted or is currently being transmitted. No fields of this BD may be writ-
ten by the user once this bit is set.
mitted frame equals the MINFLR. The PAD bytes are stored in PADs in the param-
eter RAM.
receive incoming data into the first BD in the table (the BD pointed to by TBASE).
The number of Tx BD s in this table is programmable and is determined only by the
W-bit and the overall space constraints of the dual-port RAM.
been serviced. These bits can cause interrupts if they are enabled.
15
The TxBD table must contain more than one BD in Ethernet
mode.
R
PAD
14
13
W
Freescale Semiconductor, Inc.
For More Information On This Product,
12
I
MC68360 USER’S MANUAL
11
L
Go to: www.freescale.com
TC
10
NOTE
DEF
TX DATA BUFFER POINTER
9
DATA LENGTH
HB
8
LC
7
RL
6
5
4
RC
3
2
UN
1
CSL
0