MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 585

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

LG—Rx Frame Length Violation
NO—Rx Nonoctet Aligned Frame
SH—Short Frame
CR—Rx CRC Error
OV—Overrun
CL—Collision
Data Length
Rx Data Buffer Pointer
7.10.23.19 ETHERNET TRANSMIT BUFFER DESCRIPTOR (TX BD). Data is presented
to the Ethernet controller for transmission on an SCC channel by arranging it in buffers ref-
miscuous mode, the user can use the Miss bit to quickly determine whether the frame was
destined to this station. This bit is valid only if the L bit is set.
A frame length greater than the maximum defined for this channel was recognized (only
the maximum-allowed number of bytes is written to the data buffer).
A frame that contained a number of bits not divisible by 8 was received, and the CRC
check that occurred at the preceding byte boundary generated an error.
A frame length that was less than the minimum defined for this channel was recognized.
This indication is possible only if the RSH bit is set in the PSMR.
This frame contains a CRC error.
A receiver overrun occurred during frame reception.
This frame was closed because a collision occurred during frame reception. This bit will
be set only if a late collision occurred or if the RSH bit is enabled in the PSMR. The late
collision definition is determined by the LCW bit in the PSMR.
The data length is the number of octets written by the CP into this BD’s data buffer. It is
written by the CP once as the buffer is closed.
When this BD is the last BD in the frame (L = 1), the data length contains the total number
of frame octets (including four bytes for CRC).
The receive buffer pointer, which always points to the first location of the associated data
buffer, may reside in either internal or external memory. This pointer must be divisible by
4.
0 = The frame was received because of an address recognition hit.
1 = The frame was received because of promiscuous mode.
The actual amount of memory allocated for this buffer should be
greater than or equal to the contents of the MRBLR.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Serial Communication Controllers (SCCs)