MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 309

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The following bits are used for DRAM bank properties:
PGS2–PGS0—Page Size
DPS1–DPS0—DRAM Port Size
This attribute determines the page size for the DRAM controller (see Table 6-9). The page
size is the smallest DRAM size the user needs to support with page mode capability.
For instance, PGS = 001 (256K) should be used for a 32-bit-wide memory composed of
four 256K
teen 256K
This attribute determines the DRAM bank port size (see Table 6-10). The DRAM controller
asserts the appropriate DSACKx lines according to these bits. If an MC68EC040 access
is performed using this DRAM bank and SPS = 00 or 01, the DRAM controller operates
the same way, but asserts TA instead of DSACK.
The internal DRAM address multiplexer and the page logic sup-
port only a port size of 32 bits or 16 bits. An 8-bit DRAM port size
is not allowed.
The DRAM controller does not support an external DSACKx re-
sponse for a bank on which page mode is used. Also, an exter-
nal DSACK response may not occur before RAS is asserted.
PGS2-PGS0
8 devices, a 16-bit-wide memory composed of two 256K
1 devices. In all cases, the width of the DRAMs is irrelevant.
000
001
010
011
100
101
110
110
Freescale Semiconductor, Inc.
For More Information On This Product,
A11-25(32), A10-25(16)
A11-25(32), A10-25(16)
A12-25(32), A11-25(16)
A12-25(32), A11-25(16)
A13-25(32), A12-25(16)
A13-25(32), A12-25(16)
A14-25(32), A13-25(16)
A10-25(32), A9-25(16)
Address Lines Used
DPS1–DPS0
Table 6-10. DRAM Port Size
Table 6-9. DRAM Page Size
MC68360 USER’S MANUAL
00
01
10
11
Go to: www.freescale.com
NOTES
DRAM Port Size Is 32 Bits
DRAM Port Size Is 16 Bits
External DSACKx Support
Reserved
# Address/Page in Page Compare
Result
1024 Addresses
1024 Addresses
2048 Addresses
2048 Addresses
4096 Addresses
256 Addresses
512 Addresses
512 Addresses
System Integration Module (SIM60)
8 devices, or six-