MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 388

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Serial Interface with Time Slot Assigner
7.8.2 TSA Overview
The TSA implements both the internal route selection and time-division multiplexing for mul-
tiplexed serial channels. The TSA supports the serial bus rate and format for most standard
TDM buses, including the T1 and CEPT highways, the PCM highway, and the ISDN buses
in both basic and primary rates. The two popular ISDN basic rate buses, IDL and GCI (also
known as IOM-2), are supported. An additional level of flexibility is provided by the TSA in
that it supports two TDMs. It is therefore possible to simultaneously support one T1 line and
one CEPT line, one basic rate and one primary rate ISDN channel, etc.
TSA programming is completely independent of the protocol used by the SCC or SMC. For
instance, the fact that SCC2 may programmed for the HDLC protocol has no impact on the
programming of the TSA. The purpose of the TSA is to route the data from the specified pins
to the desired SCC or SMC at the correct time. It is the job of the SCC or SMC to handle the
data it receives.
In its simplest mode, the TSA identifies the frame using one sync pulse and one clock signal
provided externally by the user. This can be enhanced to allow independent routing of the
receive and transmit data on the TDM. Additionally, the definition of a time slot need not be
limited to 8 bits or even limited to a single contiguous position within the frame. Finally, the
user may provide separate receive and transmit syncs as well as receive and transmit
clocks. These various configurations are illustrated in Figure 7-20.
7-64
MC68360 USER’S MANUAL
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