MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 292

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM60)
V—Valid
6.9.4 Port E Pin Assignment Register (PEPAR)
The PEPAR controls the I/O pins associated with the EBI. Refer to Section 4 Bus Operation
for more information about the EBI. Port E pins can be independently programmed to be
either CAS3–CAS0 or IACK6 and IACK3–IACK1; AVEC (or AVECO) or IACK5; CS3 or
IACK7; AMUX or OE; A31–A28 or WE3–WE0.
Until the low byte of PEPAR is written, the WE3–WE0/A31–A28 pins are three-stated. The
PWW bit indicates whether the low byte of PEPAR was written. PEPAR may be read or writ-
ten at any time.
Bits 15, 11, and 3—Reserved
6-48
The address space bits for 040 type MPU are:
AS8—Not Relevant for 040 Cycles
AS7—Acknowledge Access(TT1-TT0=11)
AS6—Supervisor Code Access(TT1-TT0=00, TM2-TM0=110)
AS5—Supervisor Data Access(TT1-TT0=00, TM2-TM0=101)
AS4—MMU Table search Code Access (TT1-TT0=00, TM2-TM0=100)
AS3—MMU Table search Data Access(TT1-TT0=00, TM2-TM0=011)
AS2—User Code Access(TT1-TT0=00, TM2-TM0=010)
AS1—User Data Access(TT1-TT0=00, TM2-TM0=001)
AS0—Data Cache Push Access(TT1-TT0=00, TM2-TM0=000)
For each address space bit:
This bit indicates when the contents of the breakpoint address register and breakpoint
control register pair are valid. BKPT signal will not be asserted unless the valid bit is set.
0 = A breakpoint match can occur for this address space.
1 = Mask this address space from the breakpoint match logic. No breakpoint match will
0 = Contents not valid.
1 = Contents valid.
occur if this address space is used on a bus access.
WE0–WE3
A28–A31
15
—
0
7
0
AMUX
OE/
14
0
6
0
Freescale Semiconductor, Inc.
For More Information On This Product,
SINTOUT
PWW
13
0
5
0
MC68360 USER’S MANUAL
Go to: www.freescale.com
IACK3, 6
CAS2, 3
12
0
4
0
11
—
—
0
3
0
IACK1, 2
CAS0, 1
10
0
2
0
CF1MODE
IACK7
CS7
9
0
1
0
(AVECO)/
AVEC or
RAS1DD
IACK5
IPIPE1/
8
0
0
0