MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 737

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Also, before the interrupt can be processed, the CPU32+ status register (SR) must be pro-
grammed to change the interrupt mask bits from a value of $7 to a value of $0 (or at least a
value lower than the interrupt level desired).
Next, write the PITR bits in the PITR to start the timer and wait for the interrupt.
Step 17: Test the CPM
After the SIM60 is programmed, it is time to begin testing the CPM. In order of increasing
initialization complexity, the following sub-blocks may be tested. See the initialization exam-
ples included in this manual where the blocks are described.
The SPI, SMCs, and SCCs should be tested in loopback mode before attempting to send
and receive data externally.
Step 18: Generate Interrupts with the CPM
When testing interrupts on the CPM, the user should implement this gradually. First, gener-
ate an interrupt with a timer or parallel I/O pin. Then proceed to more complicated interrupt
structures like the serial channels.
Step 19: Enable External Interrupts
The next step is to allow external devices (if any) to interrupt the QUICC. These interrupts
can enter the QUICC through the SIM60 (IRQx pins) or the CPM (parallel I/O pins with inter-
rupt capability).
Dual-Port RAM
Parallel I/O Ports A, B, and C
Baud Rate Generators
Four General-Purpose Timers
RISC Timer Tables
IDMA (without buffer chaining)
SPI (loopback mode test)
IDMA (with buffer chaining)
SMCs (loopback mode test)
SCCs (loopback mode without the time slot assigner)
SCCs (loopback mode with the time slot assigner)
The exception vector table may have been located in ROM, in
which case the PIT vector location should be initialized before
power-on reset.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Applications