MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 374

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

IDMA Channels
Single Address Destination Write . During the single address destination write cycle, the
source device is controlled by the IDMA handshake signals (DREQx, DACKx, and DONEx).
When the source device requests service from the IDMA channel, the IDMA asserts of
DACKx to allow the source device to drive data onto the data bus. The data is written to the
device or to memory selected by the address in the DAPR, the destination function codes in
the FCR, and the size in the CMR. The data bus is placed in a high-impedance state for this
write cycle. For more details about the IDMA handshake signals, see 7.6.3 Interface Signals.
7.6.4.6.3 Fast-Termination Option. While in the operand transfer phase, the IDMA sup-
ports an option to achieve a transfer in the shortest possible number of clocks (see Figure
7-16).
Using the SIM60 chip-select logic, the fast-termination option can be employed to give a fast
bus access of two clock cycles rather than the standard three-cycle access time. The fast-
termination option is described in Section 6 System Integration Module (SIM60) and in Sec-
tion 4 Bus Operation.
If the fast-termination option is used with external request burst mode, an extra IDMA cycle
results on every burst transfer. In the burst mode with fast termination selected, a new cycle
starts even if DREQx negation and DACKx assertion occur simultaneously.
7-50
NOTE: This example shows a fast termination on the write cycle. The fast termination
BEING WRITTEN
PERIPHERAL IS
PERIPHERAL IS
CYCLE STEAL
BEING READ
(OUTPUT)
(OUTPUT)
REQUEST
(OUTPUT)
(OUTPUT)
DSACKx
ECO = 0
may occur on the read, write, or both.
ECO = 1
(INPUT)
CLKO1
DREQx
DACKx
DACKx
R/W
(I/O)
Figure 7-16. Fast Termination Example
AS
Freescale Semiconductor, Inc.
For More Information On This Product,
S0
OTHER CYCLE
MC68360 USER’S MANUAL
S2
Go to: www.freescale.com
S4
S0
IDMA READ
S2
S4
S0
TERMINATION
WRITE
FAST
IDMA
S4
S0