MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 264

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM60)
6.6 BREAKPOINT LOGIC
The breakpoint logic provides an internal breakpoint address register (BKAR) and a break-
point control register (BKCR) that allow hardware breakpoints in a QUICC system. This
function is especially useful during in-field debugging activity when it is difficult to connect
an in-circuit emulator or logic analyzer to the target board. The use of the background mode
of the CPU32+, in combination with the breakpoint logic, provides a convenient and powerful
debugging capability.
When a breakpoint match occurs, the BKPT line is asserted. This can cause a BKPT excep-
tion to the CPU32+, and will set a status bit in the IDMA or SDMA that can be used to gen-
erate a maskable interrupt. The maskable interrupt may or may not terminate IDMA or
SDMA activity, depending on the bus arbitration priority of the IDMA or SDMA as compared
to the interrupt level asserted.
The breakpoint logic allows a great deal of flexibility in what constitutes a breakpoint match.
If more than one hardware breakpoint is required, then additional breakpoints may be gen-
erated externally in hardware and assert the BKPT pin.
6-20
NOTE: If the PLL is enabled and the multiplication factor is less than or equal to 4, then CLKO2–CLKO1 is
synchronized to EXTAL.
MODCK
1–0
00
01
10
11
Emulator manufacturers use the QUICC breakpoint logic in their
QUICC emulator designs. Customers using emulators should
leave the breakpoint logic available for use by the emulator man-
ufacturer, and should not configure the breakpoint logic in their
application programs.
When the QUICC is configured for a 32-bit bus, the CPU32+ can
fetch two instructions simultaneously. Since there is only one
BKPT pin, the user cannot break on each instruction, but rather
must break on both, causing the BKPT exception to be taken af-
ter the first instruction and before the second. The internal
breakpoint logic, however, can assert a breakpoint for either in-
struction individually.
Disabled
Enabled
Enabled
Enabled
PLL
Table 6-1. Default Operation Mode of the PLL
Freescale Semiconductor, Inc.
For More Information On This Product,
Prescaled by
Reserved
128
Yes
No
No
MC68360 USER’S MANUAL
Go to: www.freescale.com
Multi. Factor
Reserved
NOTE
NOTE
(MF + 1)
401
401
1
EXTAL Freq.
(Examples)
32.768 kHz
4.192 MHz
Reserved
>10 MHz
CLKIN to the
32.768 kHz
32.75 kHz
Reserved
=EXTAL
PLL
Initial Freq.
13.14 MHz
13.14 MHz
Reserved
=EXTAL
(VCO/2)