MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 114

IC MPU QUICC 25MHZ 240-FQFP

MC68EN360CAI25L

Manufacturer Part Number
MC68EN360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Series
MC68000r

Specifications of MC68EN360CAI25L

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Core Size
32 Bit
Cpu Speed
25MHz
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
No. Of Pins
240
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EN360CAI25L
Manufacturer:
APLHA
Quantity:
12 000
Part Number:
MC68EN360CAI25L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EN360CAI25L
Manufacturer:
FREESCALE
Quantity:
20 000
Bus Operation
4.4.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting
device cannot supply a vector number, it requests an automatically generated vector
(autovector). Instead of placing a vector number on the data bus and asserting DSACKx,
the device asserts AVEC to terminate the cycle. The DSACKx signals may not be asserted
4-38
* Internal arbitration may take between 0–2 clock cycles.
IACK7–IACK1
IRQ7–IRQ1
FC3–FC0
D23–D16
D31–D24
DSACKx
A31–A4
CLKO1
A3–A1
SIZ0
SIZ1
R/W
AS
DS
A0
Figure 4-27. Interrupt Acknowledge Cycle Timing
S0
Freescale Semiconductor, Inc.
S2
CYCLE
READ
For More Information On This Product,
S4
MC68360 USER’S MANUAL
Go to: www.freescale.com
S0
ARBITRATION
0–2 CLOCKS*
INTERNAL
VECTOR FROM 16-BIT PORT
VECTOR FROM 8-BIT PORT
INTERRUPT LEVEL
CPU SPACE
IACK CYCLE
1 BYTE
S1
S2
S4
S0
WRITE
STACK
S2

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