MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 785

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Applications
9.6.5.6 QUICC I/O PORTS. The functions on QUICC parallel I/O ports A, B, and C may be
used as desired in this application. However, any unused parallel I/O pins should be config-
ured as outputs so they are not left floating. Do not forget to enable the DREQ1 and DACK1
pins on port B.
9.6.6 Active SCSI Terminations
There are multiple devices that provide switchable precision SCSI bus terminations. They
are available in surface mount packages for different bus sizes. By utilizing flexible system
design techniques, enabling or disabling terminations can be accomplished in software or
hardware. Motorola's family of SCSI terminators currently includes the following devices:
For more information, refer to the individual data sheets on each part.
9.6.7 Software Configuration
The following paragraphs discuss a number of key points for a software engineer desiring
to initialize the system. The only items discussed are those that are required to enable the
previously discussed hardware configuration. See 9.1 Minimum System Configuration for
additional information.
9.6.7.1 CONFIGURING IDMA1. In this example, it is assumed that data is transferred from
the 53C90 to 32-bit-wide memory. Therefore, the source size is one byte and the destination
size is long word. The source address should be outside the 53C90 memory space but
should still access the FIFO at $02 ($04001802), and the destination address should be
$A0000000. The number of bytes to be transferred is 4 Mbytes.
9-65
• MCCS142233 (passive, 9 resistor pairs, 220 /330 )
• MCCS142234 (active, 9 bits, 110 )
• MCCS142235/36/37 (active, 18 bits, 110 , different voltages, regulators, and enables)
• MC34268 (SCSI-2 active terminator).
ICCR = $0720. The IDMA ignores the FREEZE signal, IDMA1 has priority over IDMA2
and all interrupt handlers, IDMA1 arbitration ID is 2 while IDMA2 is 0, and the system clock
operates normally within the IDMA.
FCR1 = $89. Source function code is 1000; destination function code is 1001.
SAPR1 = $04001802. Source address.
DAPR1 = $A0000000. Destination address.
BCR1 = $00400000. Byte transfer count.
CSR1 = $FF. Clear any CSR bits that are set.
CMAR1 = $FF. Enable all interrupts.
CMR1 = $8941. The 53C90 uses the control signals during the read portion of the trans-
fer. The IDMA1 uses asynchronous request mode, dual address transfer, single buffer
mode, and external request burst transfer mode. The SAPR and DAPR are incremented
according to source size (byte) and destination size (long word). Setting STR starts the
channel.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com