MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 266

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM60)
6.7.1 Initial Configuration
The QUICC has three configuration (CONFIG) pins that are sampled during system (or
power-up) reset to select the initial size of the global chip select and whether the QUICC is
in the normal (CPU32+ enabled) mode or the slave (CPU32+ disabled) mode (see Table 6-
2).
See 6.10 Memory Controller for a description of the global chip select and 6.8 Slave (Disable
CPU32+) Mode for a description of slave mode. In normal mode, the global chip select can
initially assume the boot ROM port size to be either 8, 16, or 32 bits. In the slave mode, the
global chip select can be enabled with 8, 16, or 32 bits, or the global chip select can be dis-
abled. The global chip select would normally be disabled if another QUICC or processor was
providing the boot ROM chip select function.
6.7.2 Port D
If the user configures a 16-bit data bus by driving a zero voltage on the PRTY3 pin during
system reset, then the D0–D15 pins are not used as a data bus, but are referred to as port
D. At this time, port D is not available for general-purpose I/O or any other alternate function
on the QUICC. In the future, these pins may be defined to have an additional function in 16-
bit data bus mode.
6-22
CONFIG2
/FREEZE
0
0
0
0
1
1
1
1
Configuration Pins
All accesses to the QUICC internal RAM and registers (including
MBAR) by an external master are asynchronous to the QUICC
clock. Read and write accesses are with three wait states, and
DSACK is asserted by the QUICC assuming three-wait-state ac-
cesses.
CONFIG1
/BCLRO
0
0
1
1
0
0
1
1
Freescale Semiconductor, Inc.
Table 6-2. QUICC Initial Configuration
CONFIG0
/RMC
For More Information On This Product,
0
1
0
1
0
1
0
1
MC68360 USER’S MANUAL
Slave mode; global chip select 8-bit size; MBAR at $003FF00.
Slave mode; global chip select 32-bit size; MBAR at $003FF00; not
MC68040 companion mode; BR output, BG input.
Slave mode; global chip select 16-bit size; MBAR at $003FF00.
MC68040 companion mode; global chip select 32-bit size; MBAR at
$003FF00; BR input, BG output.
CPU32+ enabled; global chip select 32-bit size; MBAR at $003FF00.
CPU32+ enabled; global chip select 16-bit size; MBAR at $003FF00.
Slave mode; global chip select disabled; MBAR at $003FF04.
CPU32+ enabled; global chip select 8-bit size; MBAR at $003FF00.
Go to: www.freescale.com
NOTE
Result