MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 634

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Management Controllers (SMCs)
7.11.14.6 SMC MONITOR CHANNEL TX BD. The CP reports the information about the
monitor channel transmit byte using this BD.
R—Ready
L—Last (EOM)
AR—Abort Request
Bits 12–10—Reserved
DATA—Data Field
7.11.14.7 SMC C/I CHANNEL RECEIVE BUFFER DESCRIPTOR (RX BD). The
reports information about the C/I channel receive byte using this BD.
E—Empty
Bits 14–8,1-0—Reserved
7-310
15
15
This bit is valid only when the SMC implements the monitor channel protocol. When this
bit is set, the SMC will first transmit the buffer’s data and then transmit the end-of-mes-
sage (EOM) indication on the E-bit.
This bit is valid only when the SMC implements the monitor channel protocol. This bit is
set by the SMC when an abort request is received on the A-bit. The SMC transmitter will
transmit the EOM on the E-bit after an abort request is received.
These bits should be cleared by the user.
The data field contains the data to be transmitted by the SMC on the monitor channel.
These bits should be cleared by the user.
R
E
0 = This bit is cleared by the CP after transmission. The Tx BD is now available to the
1 = This bit is set by the CPU32+ core to indicate that the data byte associated with
0 = This bit is cleared by the CP to indicate that data byte associated with this BD is
1 = This bit is set by the CPU32+ core to indicate that the data byte associated with
14
14
L
CPU32+ core.
this BD is ready for transmission.
now available to the CPU32+ core.
this BD has been read.
AR
13
13
Additional data received will be discarded until the E-bit is set.
12
12
11
—
11
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Freescale Semiconductor, Inc.
For More Information On This Product,
10
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
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9
9
—
NOTE
8
8
7
7
6
6
5
5
C/I DATA
4
4
DATA
3
3
2
2
1
1
—
CP
0
0