MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 132

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
master at the same time, the one having the highest priority becomes bus master first. The
sequence of the protocol in normal slave mode is as follows:
The state machine for the normal slave mode arbitration is shown in Figure 4-38.
In 68040 companion mode, the QUICC changes its bus arbitration sequence to match that
needed by the 68040. It is as follows:
4-56
1. The QUICC asserts BR.
2. The QUICC waits for the assertion of BG and the negation of BGACK to indicate that
3. The QUICC asserts BGACK to indicate that it has assumed the bus.
1. The QUICC asserts BG continuously whenever the QUICC does not need the bus.
2. When the QUICC needs the bus, and the 68040 is not requesting the bus, it will deas-
the bus is available.
sert BG from the 68040 and assert BB to indicate that it has assumed the bus. If the
68040 then requests the bus using the BR pin, while the QUICC is asserting BB, the
BR040ID bits in the MCR will be used to determine if the 68040 has a high enough bus
request priority to cause the QUICC to give up the bus (i.e. deassert BB and assert
BG.)
NOTE: BGACK is only asserted by QUICC during the state "QUICC Owns Bus", otherwise BGACK is
QUICC NO LONGER NEEDS BUS
REFRESH DOES NOT NEED BUS
EXTERNAL
BUS IDLE
HALT ASSERTED AND DRAM
three-stated by the QUICC.
Figure 4-38. Slave Mode Bus Arbitration State Machine
OR
NEGATED
IDLE
BR
Freescale Semiconductor, Inc.
For More Information On This Product,
EXTERNAL MASTER ACCESS TO DUAL PORT RAM
HALT IS ASSERTED AND DRAM REFRESH
MC68360 USER’S MANUAL
DOES NOT REQUIRE EXTERNAL BUS
Go to: www.freescale.com
QUICC REQUIRES EXTERNAL BUS
BR NEGATED
OWNS BUS
ASSERTED
BGACK
QUICC
QUICC STILL NEEDS BUS
BG = 0
WAITING FOR
ASSERTED
QUICC
BUS
BR
BG = 1