MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 669

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.13.8.2 CENTRONICS CHANNEL TRANSMISSION. The Centronics transmitter supports
the same general data structure that is used by the SCCs for other protocols. When the STR
bit in the PIP configuration register is set, the Centronics controller will process the next
buffer descriptor (BD) in the Centronics transmitter BD table. If the BD is ready, the Centron-
ics transmitter will fetch the data from the memory and start sending it to the printer. If the
status mask bits are set in the SMASK register, the printer status line (Select, PError and
Fault) will be checked before each transfer. In this case, the user should configure PB1,2,3
pins as general purpose inputs and connect them to Select, PError, and Fault respectively.
data lines and will generate the strobe pulse if previous data was acknowledged and the
minimum setup time was met. The strobe pulse width and the setup time parameters are
programmed by the PIP Timing Parameter Register (PTPR). A single data frame may span
several BDs. A maskable interrupt can be generated after the processing of each BD.
7.13.8.3 CENTRONICS TRANSMITTER MEMORY MAP. When configured to operate in
Centronics Transmit mode, the QUICC overlays the structure illustrated in Table 7-17 with
the SMC2 parameter RAM area.
For each transfer the Centronics controller will output the data on the Centronics interface
• Supports Closed Loop Handshake for Higher Data Transfer Rates
• Supports Centronics Transmitter and Receiver Operating Modes
• Supports Bidirectional Centronics (P1284)
• Flexible Message-Oriented Data Structure
• Flexible Control Character Comparison (Receiver)
• Flexible Timing Modes
• Programmable timing parameters
PIP Base+00
PIP Base+02
PIP Base+04
PIP Base+05
PIP Base+06
PIP Base+08
PIP Base+0C
PIP Base+10
PIP Base+12
PIP Base+14
PIP Base+18
PIP Base+1C
PIP Base+20
PIP Base+22
PIP Base+24
Address
Table 7-17. Centronics Transmitter Parameter RAM
Res
TBASE
CFCR
SMASK
Res
Res
Res
Res
Res
Res
TSTATE
T_PTR
TBPTR
T_CNT
TTEMP
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Word
Word
Byte
Byte
Word
Long
Long
Word
Word
Long
Long
Long
Word
Word
Long
Width
Reserved
Tx Buffer Descriptors Base Address
Centronics Function Code
Status Mask
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Tx Internal State
Tx Internal Data Pointer
Tx Buffer Descriptor Pointer
Tx Internal Byte Count
Tx Temp
Description
Parallel Interface Port (PIP)