MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 260

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM60)
(CLKO1 and CLKO2). The PLL synchronizes these clock signals to each other. These clock
signals are discussed in the following paragraphs.
6.5.5.1 SPCLK. SPCLK is supplied to the PIT and SWT sub-modules in the SIM60. SPCLK
is always the EXTAL frequency or EXTAL/128, depending on the configuration of the divide-
by-128 prescaler. When EXTAL frequency > 10 MHz is selected by configuration pins
(MODCK1-MODCK0 = 01), then the PLL is clocked with the EXTAL frequency and SPCLK
is EXTAL/128. (i1616.e. When MODCK is 11 --> SPCLK is equal to EXTAL).
6.5.5.2 GENERAL SYSTEM CLOCK. This basic clock is supplied to all other modules and
sub-modules on the QUICC, including the CPU32+, the RISC controller, and most other fea-
tures in the communication processor module (CPM). The general system clock also sup-
plies the SIMCLK to the SIM60 in normal device operation. The general system clock is the
same as the CLKO1 frequency, and the CLKO2 signal is 2 the general system clock in nor-
mal device operation. The general system clock defaults to VCO/2 = 25 MHz (assuming a
25-MHz system frequency).
The frequency of the general system clock can be changed dynamically with the CDVCR,
as shown in Figure 6-7. This configuration is called slow-go mode.
The general system clock can be operated at three frequencies. Normal operation is the
highest frequency (25 MHz in a 25-MHz system). The general system clock can also be
operated at a low frequency and a high frequency. The definition of low is made in the DFNL
value in CDVCR; the definition of high is made in the DFNH value in CDVCR.
The frequency of the general system clock can be changed dynamically by software. The
user may simply cause the general system clock to switch to its low frequency. However, in
some applications, there is a need for high frequency during certain periods. An example is
in interrupt routines, etc., that need more performance than the low frequency operation, but
must consume less power than in normal operation. The SIM60 allows a method to auto-
matically switch between low and high frequency operation.
6-16
NOTES:
1. NORMAL = (CSRC = 0) OR (INTEN2–INTEN0 < INTERRUPT) OR (RRQEN & RISC NOT IDLE)
2. LOW POWER = NORMAL
VCO/2 (25 MHz)
DFNL DIVIDER
DFNH DIVIDER
Figure 6-7. General System Clock Select
Freescale Semiconductor, Inc.
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DFNH <> 00
DFNH = 0
NORMAL
LOW POWER
GENERAL SYSTEM
CLOCK