MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 150

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
5.3 INSTRUCTION SET
The following paragaphs describe the CPU32+ instruction set. A description of the instruc-
tion format, the operands used by the instructions, and a summary of the instructions by cat-
egory are included. Complete programming information is provided in the M68000PM/AD,
M68000 Family Programmer’s Reference Manual.
The CPU32+ instructions include machine functions for all the following operations:
The large instruction set encompasses a complete range of capabilities and, combined with
the enhanced addressing modes, provides a flexible base for program development.
The instruction set of the CPU32+ is very similar to that of the MC68020 (see Table 5-1).
The following M68020 instructions are not implemented on the CPU32+:
The CPU32+ traps on unimplemented instructions or illegal effective addressing modes,
allowing user-supplied code to emulate unimplemented capabilities or to define special-pur-
pose functions. However, Motorola reserves the right to use all currently unimplemented
instruction operation codes for future M68000 core enhancements.
5-8
• Data Movement
• Arithmetic Operations
• Logical Operations
• Shifts and Rotates
• Bit Manipulation
• Conditionals and Branches
• System Control
BFxx
CALLM, RTM — Call Module, Return Module
CAS, CAS2
cpxxx
PACK, UNPK — Pack, Unpack BCD Instructions
15
T1
ENABLE
TRACE
T0
SUPERVISOR/USER
14
STATE
13
S
— Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU,
— Compare and Set (Read-Modify-Write Instructions)
— Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE,
SYSTEM BYTE
12
0
BFFFO, BFINS, BFSET, BFTST)
cpSAVE, cpScc, cpTRAPcc)
Freescale Semiconductor, Inc.
11
For More Information On This Product,
0
Figure 5-5. Status Register
10
I2
PRIORITY MASK
MC68360 USER’S MANUAL
INTERRUPT
Go to: www.freescale.com
9
I1
8
I0
0
7
0
6
(CONDITION CODE REGISTER)
5
0
EXTEND
USER BYTE
4
X
NEGATIVE
3
N
ZERO
2
Z
OVERFLOW
1
V
CARRY
0
C