MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 681

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.14.1 Parallel I/O Key Features
The parallel I/O ports contain the following key features:
7.14.2 Parallel I/O Overview
Each pin in the I/O ports may be configured as a general-purpose I/O pin or as a dedicated
peripheral interface pin. Port A is shared with the SCC RXD and TXD pins, the bank of
clocks pins, and some TDM pins. Port B is shared with the PIP and other functions such as
the IDMA, SMC, and SPI pins. Port C is shared with the RTS, CTS, and CD pins of the SCCs
as well as some TDM pins. Port C is unique in that its pins may generate interrupts to the
CPM interrupt controller.
Each pin may be configured as an input or output and has a latch for data output. Each pin
may be read or written at any time. Each pin may be configured as general-purpose I/O or
as a dedicated peripheral pin.
Port A and port B have pins that can be configured as open-drain—that is, the pin may be
configured in a wired-OR configuration on the board. The pin drives a zero voltage, but
three-states when driving a high voltage.
7.14.3 Port A Pin Functions
Refer to Table 7-19 for the default description of all port A pin options. The pins marked in
boldface can have open-drain capability. Each of the 16 port A pins is independently con-
figured as a general-purpose I/O pin if the corresponding port A pin assignment register
• Port A Is 16 Bits
• Port B Is 18 Bits
• Port C Is 12 Bits
• All Ports Are Bidirectional
• All Ports Have Alternate On-Chip Peripheral Functions
• All Ports Are Three-Stated at System Reset
• All Pin Values May Be Read While Pin Is Connected to an On-Chip Peripheral
• Port A and Port B Offer Open-Drain Capability
• Port C Offers 12 Interrupt Input Pins
The port pins do not have internal pullup resistors.
Due to the significant flexibility of the QUICC’s CPM, many ded-
icated peripheral functions are multiplexed onto ports A, B, and
C. The functions are grouped in such a way as to maximize the
usefulness of the pins in the greatest number of QUICC applica-
tions. The reader may not obtain a full understanding of the pin
assignment capability described in this section until attaining an
understanding of the CPM peripherals themselves.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
Parallel I/O Ports