MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 556

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
7.10.21.11 TRANSPARENT EVENT REGISTER (SCCE). The SCCE is called the trans-
parent event register when the SCC is operating as a transparent controller. It is a 16-bit reg-
ister used to report events recognized by the transparent channel and to generate interrupts.
On recognition of an event, the transparent controller will set the corresponding bit in the
transparent event register. Interrupts generated by this register may be masked in the trans-
parent mask register.
The transparent event register is a memory-mapped register that may be read at any time.
A bit is reset by writing a one (writing a zero does not affect a bit’s value). More than one bit
may be reset at a time. All unmasked bits must be reset before the CP will negate the inter-
nal interrupt request signal. This register is cleared at reset.
Bits 15–13, 9–8, 6–5—Reserved
GLr—Glitch on Rx
GLt—Glitch on Tx
DCC—DPLL CS Changed
GRA—Graceful Stop Complete
TXE—Tx Error
RCH—Receive Character
BSY—Busy Condition
7-232
15
A clock glitch was detected by this SCC on the receive clock.
A clock glitch was detected by this SCC on the transmit clock.
The carrier sense status as generated by the DPLL has changed state. The real-time sta-
tus may be found in SCCS. This is not the CD pin status, which is reported elsewhere,
and is only valid when the DPLL is used.
A graceful stop, which was initiated by the GRACEFUL STOP TRANSMIT command, is
now complete. This bit is set as soon the transmitter has finished transmitting any frame
that was in progress when the command was issued. It will be set immediately if no frame
was in progress when the command was issued.
An error (CTS lost or underrun) occurred on the transmitter channel.
A byte or long word has been received and written to the buffer. This depends on the set-
ting of the RFW bit in the GSMR.
A byte/long-word was received and discarded due to lack of buffers. The receiver will re-
sume reception after an ENTER HUNT MODE command.
14
—
13
GLr
12
GLt
11
Freescale Semiconductor, Inc.
For More Information On This Product,
DCC
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
—
9
—
8
GRA
7
—
6
—
5
TXE
4
RCH
3
BSY
2
TX
1
RX
0