MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 230

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
In the following equations, negative tail values are used to negate the effects of a slower
bus. The equations are generalized, however, so that they may be used on any speed bus
with any tail value.
where:
Note that many instructions listed as having negative tails are change-of-flow instructions
and that the bus speed used in the calculation is that of the new instruction stream.
5.7.2 Instruction Timing Tables
The following assumptions apply to the times shown in the subsequent tables:
Three values are listed for each instruction and addressing mode:
Head:
Tail:
Cycles: Four numbers per entry, three contained in parentheses. The outer number is the
As an example, consider an ADD.L (12, A3, D7.W
Paragraph 5.7.2.5 Arithmetic/Logic Instructions shows that the instruction has a head = 0, a
tail = 0, and cycles = 2 (0/1/0). However, in indexed address register indirect addressing
mode, additional time is required to fetch the EA. Paragraph 5.7.2.1 Fetch Effective Address
gives addressing mode data. For (d
0). Because this example is for a long access and the fetch EA table lists data for word
5-88
NEW_TAIL
IF ((NEW_CLOCK – 4) > 0) THEN
ELSE
NEW_TAIL/NEW_CYCLE
OLD_TAIL/OLD_CYCLE
NEW_CLOCK
1. A 16-bit data bus is used for all memory accesses (CPU32+ in 16-bit mode).
2. Memory access times are based on two-clock bus cycles with no wait states.
3. The instruction pipeline is full at the beginning of the instruction and is refilled by the
end of the instruction.
NEW_CYCLE = OLD_CYCLE
NEW_CYCLE = OLD_CYCLE
The number of cycles available at the beginning of an instruction to complete a
previous instruction write or to perform a prefetch.
The number of cycles an instruction uses to complete a write.
minimum number of cycles required for the instruction to complete. Numbers
within the parentheses represent the number of bus accesses performed by the
instruction. The first number is the number of operand read accesses performed
by the instruction. The second number is the number of instruction fetches per-
formed by the instruction, including all prefetches that keep the instruction and the
instruction pipeline filled. The third number is the number of write accesses per-
formed by the instruction.
OLD_TAIL
is the number of clocks per cycle at the slower speed
is the value listed in the instruction timing tables
is the adjusted tail/cycle at the slower speed
(NEW_CLOCK – 2)
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
(NEW_CLOCK – 2)
(NEW _CLOCK – 2)
Go to: www.freescale.com
8
, An, Xn.Sz Scale), head = 4, tail = 2, cycles = 8 (2/1/
(NEW_CLOCK – 4)
4), D2 instruction.