MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 59

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

is the general system clock. CLKO2 is 2 CLKO1 if the on-chip clock synthesizer PLL is
used, and is 1 CLKO1 otherwise.
2.1.10.2 CRYSTAL OSCILLATOR (EXTAL, XTAL). These two pins are the connections
for an external crystal to the internal oscillator circuit. If an external oscillator is used, it
should be connected to EXTAL, with XTAL left open.
2.1.10.3 EXTERNAL FILTER CAPACITOR (XFC). This pin is used to add an external
capacitor to the filter circuit of the PLL. The capacitor should be connected between XFC
and VCCSYN.
2.1.10.4 CLOCK MODE SELECT (MODCK1–MODCK0). The state of these active-high
input signals during reset selects the type of external clock that is used by the PLL in the
clock synthesizer to generate the system clocks. Table 2-5 lists the default values of the
PLL.
2.1.11 Instrumentation and Emulation Signals
These signals are used for test or software debugging. Refer to Section 5 CPU32+ for more
information on these signals.
2.1.11.1 INSTRUCTION FETCH/DEVELOPMENT SERIAL INPUT (IFETCH/DSI). This
active-low output signal indicates when the CPU32+ is performing an instruction word
prefetch and when the instruction pipeline has been flushed. Additionally, this signal is the
serial input to the CPU32+ in its background debug mode to issue background commands,
etc.
2.1.11.2 INSTRUCTION PIPE/DEVELOPMENT SERIAL OUTPUT (IPIPE0/DSO). This
active-low output signal is used to track movement of words through the instruction pipeline.
Additionally, this signal is the serial output from the CPU32+ in its background debug mode
to issue background status, etc.
2.1.11.3 INSTRUCTION PIPE/ROW ADDRESS SELECT DOUBLE-DRIVE (IPIPE1/
RAS1DD). This active-low output signal is used to track movement of words through the
instruction pipeline. This signal also functions as a second output of the RAS1 signal to
increase fanout capability.
2.1.11.4 BREAKPOINT/DEVELOPMENT SERIAL CLOCK (BKPT/DSCLK). This
low input signal is used to signal a hardware breakpoint to the CPU32+. Additionally, this
1 This mode is reserved.
MODCK
1–0
00
01
10
11
1
Disabled
Enabled
Enabled
Enabled
PLL
Table 2-5. Default Operation Mode of the PLL
Freescale Semiconductor, Inc.
Prescaled by
Reserved
For More Information On This Product,
128
Yes
No
No
MC68360 USER’S MANUAL
Go to: www.freescale.com
Multi. Factor
Reserved
(MF + 1)
401
401
1
EXTAL Freq.
(examples)
32.768 kHz
4.192 MHz
Reserved
>10 MHz
CLKIN to the
32.768 kHz
32.75 kHz
Reserved
=EXTAL
PLL
Signal Descriptions
Initial Freq.
13.14 MHz
13.14 MHz
Reserved
=EXTAL
(VCO/2)
active-