MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 186

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
tor table entry number 14. The stacked PC is the address of the RTE instruction that
discovered the format error.
5.5.2.8 ILLEGAL OR UNIMPLEMENTED INSTRUCTIONS. An instruction is illegal if it con-
tains a word bit pattern that does not correspond to the bit pattern of the first word of a legal
CPU32+ instruction, if it is a MOVEC instruction that contains an undefined register specifi-
cation field in the first extension word, or if it contains an indexed addressing mode exten-
sion word with bits 5–4 = 00 or bits 3–0
If an illegal instruction is fetched during instruction execution, an illegal instruction exception
occurs. This facility allows the operating system to detect program errors or to emulate
instructions in software.
Word patterns with bits 15–12 = 1010 (referred to as A-line opcodes) are unimplemented
instructions. A separate exception vector (vector 10, offset $28) is given to unimplemented
instructions to permit efficient emulation.
Word patterns with bits 15–12 = 1111 (referred to as F-line opcodes) are used for M68000
family instruction set extensions. They can generate an unimplemented instruction excep-
tion caused by the first extension word of the instruction or by the addressing mode exten-
sion word. A separate F-line emulation vector (vector 11, offset $2C) is used for the
exception vector.
All unimplemented instructions are reserved for use by Motorola for enhancements and
extensions to the basic M68000 architecture. Opcode pattern $4AFC is defined to be illegal
on all M68000 family members. Those customers requiring the use of an unimplemented
opcode for synthesis of "custom instructions," operating system calls, etc., should use this
opcode.
Exception processing for illegal and unimplemented instructions is similar to that for traps.
The instruction is fetched and decoding is attempted. When the processor determines that
execution of an illegal instruction is being attempted, exception processing begins. No reg-
isters are altered.
Exception processing follows the regular sequence. The vector number is generated to refer
to the illegal instruction vector or in the case of an unimplemented instruction, to the corre-
sponding emulation vector. The illegal instruction vector number, current PC, and a copy of
the SR are saved on the supervisor stack, with the saved value of the PC being the address
of the illegal or unimplemented instruction.
5.5.2.9 PRIVILEGE VIOLATIONS. To provide system security, certain instructions can be
executed only at the supervisor access level. An attempt to execute one of these instructions
at the user level will cause an exception. The privileged exceptions are as follows:
5-44
• AND Immediate to SR
• EOR Immediate to SR
• LPSTOP
• MOVE from SR
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
0000.