MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 501

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.10.17.7.2 Reception Errors. The following paragraphs describe various types of HDLC
reception errors.
Overrun Error . The HDLC controller maintains an internal FIFO; for receiving data. The CP
begins programming the SDMA channel (if the data buffer is in external memory) and updat-
ing the CRC when 8 or 32 bits (according to the RFW bit in the GSMR) are received in the
FIFO. When a receive FIFO overrun occurs, the channel writes the received data byte to the
internal FIFO over the previously received byte. The previous data byte and the frame status
are lost. The channel closes the buffer with the overrun (OV) bit in the BD set and generates
the RXF interrupt if it is enabled. The receiver then enters the hunt mode.
Even if the overrun occurs during a frame whose address is not matched in the address rec-
ognition logic, an Rx BD with data length two will be opened to report the overrun, and the
RXF interrupt will be generated if it is enabled.
CD Lost During Frame Reception . When this error occurs, the channel terminates frame
reception, closes the buffer, sets the CD bit in the Rx BD, and generates the RXF interrupt
if it is enabled. This error has the highest priority. The rest of the frame is lost, and other
errors are not checked in that frame. The receiver then enters the hunt mode.
Abort Sequence . An abort sequence is detected by the HDLC controller when seven or more
consecutive ones are received. When this error occurs and the HDLC controller is currently
receiving a frame, the channel closes the buffer by setting the AB bit in the Rx BD and gen-
erates the RXF interrupt (if enabled). The channel also increments the abort sequence
counter. The CRC and nonoctet error status conditions are not checked on aborted frames.
The receiver then enters hunt mode.
If the HDLC controller is not currently receiving a frame when an abort is received, no indi-
cation is given to the user.
Nonoctet Aligned Frame . When this error occurs, the channel writes the received data to the
data buffer, closes the buffer, sets the Rx nonoctet aligned frame (NO) bit in the Rx BD, and
generates the RXF interrupt (if enabled). The CRC error status should be disregarded on
nonoctet frames. After a nonoctet aligned frame is received, the receiver enters hunt mode.
(An immediately following back-to-back frame will still be received.) The nonoctet data may
be derived from the last word in the data buffer as follows:
MSB
If the data buffer swapping option is used (MOT bit cleared in the
RFCR), then the above diagram refers to the last byte of the data
buffer, not the last word. In HDLC, the LSB of each octet is trans-
mitted first, and the MSB of the CRC is transmitted first.
<--------VALID DATA------->
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
1
Serial Communication Controllers (SCCs)
0
<-------NONVALID DATA------->
LSB
0