MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 657

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The PIP shares several registers with the SMC2 serial channel. SMC2 is not available and
should not be enabled if the PIP is used. If SMC2 is enabled, erratic behavior will occur.
7.13.3 General-Purpose I/O Pins (Port B)
In this configuration, the PIP is not used, but rather operates as general-purpose parallel I/
O port B. See 7.14.7 Port B Registers for more details.
7.13.4 Interlocked Data Transfers
In the interlocked handshake mode, the PIP may be configured as a transmitter or a
receiver. This configuration allows a fast connection between QUICCs, and may be used for
the P1284-protocol advanced byte transfer mode.
The interlocked handshake mode may be controlled by the RISC or the CPU32+ core. Oper-
ation using the RISC requires BDs and parameter RAM initialization very similar to the other
serial channels. Data is then stored in the buffers using one of the SDMA channels (one of
the available channels from SMC2). Operation by the CPU32+ core is performed by soft-
ware-controlled reads and writes from/to the PIP data register upon interrupt request.
When configured as a transmitter, the STBO pin (PB16) is used as a strobe output (STB)
handshake control signal, and the STBI pin (PB17) is used as an acknowledge (ACK) input.
When configured as a receiver, the PIP generates the ACK signal on the STBO pin and
inputs the STB signal on the STBI pin.
Bits PB16 and PB17 in the port B data direction register (PBDIR) and the port B data register
(PBDAT) corresponding to STBO and STBI are not valid and are ignored by the PIP in the
interlocked handshake mode.
When the PIP is in this mode and is configured as a transmitter, the RISC controller loads
data into the output latch when it receives a request to begin transfers from the host proces-
sor (see Figure 7-85). Once data is loaded, after a programmable setup time, the STB signal
is asserted (low). Then when ACK is sampled as low, the data is transmitted, followed by
the STB being negated (high). STB remains high until new data is loaded into the output
latch and ACK is negated (high).
When the PIP is configured as a receiver, input data is latched when the STB signal is sam-
pled as low. The ACK signal is then asserted. ACK will be negated (high) when the data has
been removed from the input latch.
At the time of writing, RISC operation of the PIP has not been
fully defined. The user should use the CPU32+ core operation
mode, until such time as RISC microcode becomes available or
the full PIP microcode is available in the RISC internal ROM.
Please contact the local Motorola sales representative to obtain
the current status of the PIP RISC microcode. In the following
description, the RISC reads and writes of the data register are
replaced by CPU32+ core reads and writes.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Parallel Interface Port (PIP)