MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 654

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Peripheral Interface (SPI)
7.12.7 SPI Slave Example
The following list is an initialization sequence for use of the SPI as a slave. It is very similar
to the SPI master example except that the SPISEL pin is used, rather than a general-pur-
pose I/O pin.
7-330
12. Write $00000020 to the CIMR to allow the SPI to generate a system interrupt.
13. Write $0370 to SPMODE to enable normal operation (not loopback), master
14. Write PBDAT bit 0 with zero to assert the SPI select pin.
15. Set the STR bit in the SPCOM to start the transfer.
1. The SDCR (SDMA Configuration Register) should be initialized to $0740, rather than
2. Configure the port B pins to enable the SPIMOSI, SPIMISO, SPISEL, and SPICLK
3. Write RBASE and TBASE in the SPI parameter RAM to point to the Rx BD and Tx
4. Program the CR to execute the INIT RX & TX PARAMS command for this channel.
5. Write RFCR with $18 and TFCR with $18 for normal operation.
6. Write MRBLR with the maximum number of bytes per receive buffer. For this case,
7. Initialize the Rx BD. Assume the Rx data buffer is at $00001000 in main memory.
8. Initialize the Tx BD. Assume the Tx data buffer is at $00002000 in main memory
9. Write $FF to the SPIE to clear any previous events.
10. Write $37 to the SPIM to enable all possible SPI interrupts.
11. Write $00000020 to the CIMR to allow the SPI to generate a system interrupt. (The
(The CICR should also be initialized.)
mode, SPI enabled, 8-bit characters, and the fastest speed possible.
being left at its default value of $0000.
pins. Write PBPAR bits 0, 1, 2, and 3 with ones. Write PBDIR bits 0, 1, 2, and 3
with ones. Write PBODR bits 0, 1, 2, and 3 with zeros.
BD in the dual-port RAM. Assuming one Rx BD at the beginning of dual-port RAM
and one Tx BD following that Rx BD, write RBASE with $0000 and TBASE with
$0008.
For instance, to execute this command for SCC1, write $0001 to the CR. This com-
mand causes the RBPTR and TBPTR parameters of the serial channel to be updated
with the new values just programmed into RBASE and TBASE.
assume 16 bytes, so MRBLR = $0010.
Write $B000 to Rx_BD_Status. Write $0000 to Rx_BD_Length (not required—
done for instructional purposes only). Write $00001000 to Rx_BD_Pointer.
and contains five 8-bit characters. Write $B800 to Tx_BD_Status. Write $0005 to
Tx_BD_Length. Write $00002000 to Tx_BD_Pointer.
After 5 bytes have been transmitted, the Tx BD is closed. Addi-
tionally, the receive buffer is closed after 5 bytes have been re-
ceived because the L-bit of the Tx BD was set.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE