MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 579

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Serial Communication Controllers (SCCs)
after 64 byte times, then no retransmission is performed, and the buffer is closed with an LC
error indication.
If a collision occurs during frame reception, the reception is stopped. This error will be
reported in the BD only if the length of this frame is greater than or equal to the MINFLR or
if the RSH mode is enabled in the PSMR.
7.10.23.15 INTERNAL AND EXTERNAL LOOPBACK. Both internal and external loop-
back are supported by the Ethernet controller. In loopback mode, both of the SCC FIFOs
are used, and the channel actually operates in a full-duplex fashion. Both internal and exter-
nal loopback are configured using combinations of the LPB bit in the PSMR and the DIAG
bits in the GSMR. Because of the full-duplex nature of the loopback operation, the perfor-
mance of the other SCCs will be degraded.
Internal loopback disconnects the SCC from the SI. The receive data is connected to the
transmit data, and the receive clock is connected to the transmit clock. Both FIFOs are used.
The transmitted data from the transmit FIFO is received immediately into the receive FIFO.
There is no heartbeat check in this mode. In this mode TENA should be configured to be a
general purpose output.
(PCPAR[0]=0, PCDIR[0]=1, PCDAT[0]=0) and the HBC bit in the PSMR should be 0.
In external loopback operation, the Ethernet controller listens for receive data from the EEST
at the same time that it is transmitting.
7.10.23.16 ETHERNET ERROR-HANDLING PROCEDURE. The
Ethernet
controller
reports frame reception and transmission error conditions using the channel BDs, the error
counters, and the Ethernet event register.
7.10.23.16.1 Transmission Errors. The following paragraphs describe various types of
Ethernet transmission errors.
Transmitter Underrun . If this error occurs, the channel sends 32 bits that ensure a CRC
error, terminates buffer transmission, closes the buffer, sets the UN bit in the Tx BD, and
sets TXE in the Ethernet event register. The channel will resume transmission after recep-
tion of the RESTART TRANSMIT command.
Carrier Sense Lost During Frame Transmission . When this error occurs and no collision is
detected in this frame, the channel sets the CSL bit in the Tx BD, sets TXE in the Ethernet
event register, and continues the buffer transmission normally. No retries are performed as
a result of this error.
Retransmission Attempts Limit Expired . When this error occurs, the channel terminates
buffer transmission, closes the buffer, sets the RL bit in the Tx BD, and sets TXE. The chan-
nel will resume transmission after reception of the RESTART TRANSMIT command.
Late Collision . When this error occurs, the channel terminates buffer transmission, closes
the buffer, sets the LC bit in the Tx BD, and sets TXE. The channel will resume transmission
after reception of the RESTART TRANSMIT command.
MC68360 USER’S MANUAL
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