MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 414

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Interface with Time Slot Assigner
7.8.5.6.3 SIRP When RDM = 10 (Two Static TDMs). •This is the simplest case, since each
7.8.5.6.4 SIRP When RDM = 11 (Two Dynamic TDMs). •In this case, each pointer is con-
7.8.6 SI IDL Interface Support
The IDL interface is a full-duplex ISDN interface used to connect a physical layer device to
the QUICC. The QUICC supports both the basic rate and the primary rate of the IDL bus. In
the basic rate of IDL, data on three channels, B1, B2, and D, is transferred in a 20-bit frame,
providing 160-kbps full-duplex bandwidth. The QUICC is an IDL slave device that is clocked
by the IDL bus master (physical layer device) and has separate receive and transmit sec-
tions. Because the QUICC can support two TDMs, it can actually support two independent
IDL buses using separate clocks and sync pulses as shown in Figure 7-31.
7-90
If its V-bit is set, TbPTR contains the address of the Tx entry currently active. The SI RAM
transmit address block in use is 192–255, and CROTa = 1 in SISTR.
RaPTR contains the address of the RXa entry currently active.
RbPTR contains the address of the RXb entry currently active.
TaPTR contains the address of the TXa entry currently active.
TbPTR contains the address of the TXb entry currently active.
RaPTR contains the address of the RXa entry currently active. If the pointer has a value
from 0–15, the current-route RAM is SI RAM address block 0–31, and CRORa = 0 in SIS-
TR. If the pointer has a value from 16–31, the current-route RAM is SI RAM address block
32–63, and CRORa = 1 in SISTR.
RbPTR contains the address of the RXb entry currently active. If the pointer has a value
from 0–15, the current route RAM is SI RAM address block 64–95, and CRORb = 0 in SIS-
TR. If the pointer has a value from 16–31, the current-route RAM is SI RAM address block
96–127, and CRORb = 1 in SISTR.
TaPTR contains the address of the TXa entry currently active. If the pointer has a value
from 0–15, the current route RAM is SI RAM address block 128–159, and CROTa = 0 in
SISTR. If the pointer has a value from 16–31, the current-route RAM is SI RAM address
block 160–191, and CROTa = 1 in SISTR.
TbPTR contains the address of the TXb entry currently active. If the pointer has a value
from 0–15, the current-route RAM is SI RAM address block 192–223, and CROTb = 0 in
SISTR. If the pointer has a value from 224–255, the current-route RAM is SI RAM address
block 160–191, and CROTb = 1 in SISTR.
pointer is continuously used and has only one function.
tinuously used, but points to different sections of the SI RAM, depending on whether
the pointer’s value is in the first half (0–15) or the second half (16–31).
Freescale Semiconductor, Inc.
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