MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 660

IC MPU QUICC 25MHZ 240-FQFP

MC68EN360CAI25L

Manufacturer Part Number
MC68EN360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Series
MC68000r

Specifications of MC68EN360CAI25L

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Core Size
32 Bit
Cpu Speed
25MHz
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
No. Of Pins
240
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
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MC68EN360CAI25L
Manufacturer:
APLHA
Quantity:
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Part Number:
MC68EN360CAI25L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EN360CAI25L
Manufacturer:
FREESCALE
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Parallel Interface Port (PIP)
The BUSY signal is multiplexed onto PB0; therefore, it is not possible to use the BUSY sig-
nal with a full 16-bit PIP interface. BUSY can be used with the standard 8-bit PIP interface
to implement Centronics functions.
When in the pulsed handshake mode, the PIP transmitter may be configured to ignore the
BUSY signal or to suspend the assertion of the STB output until the receiver’s BUSY signal
is negated.
7.13.5.2 PULSED HANDSHAKE TIMING. The pulsed handshake mode transmitter timing
is shown in Figure 7-88. In the pulsed handshake mode, four Centronics receive timing
options select the relative timing of the BUSY signal to the ACK signal.
The timing parameters for the pulsed handshake mode are governed by two user-program-
mable timing parameters, TPAR1 and TPAR2. Each parameter defines an interval from 1 to
256 system clocks. Figure 7-89 through Figure 7-92 show the definition of TPAR1 and
TPAR2 in the four receive modes.
7-336
DATA
STB
TRANSMITTER
TRANSMITTER
RECEIVER
RECEIVER
(BUSY)
DATA
STBO
STBO
(ACK)
(STB)
PB0
Figure 7-87. Pulsed Handshake Busy Signal
Figure 7-88. Centronics Transmitter Timing
Freescale Semiconductor, Inc.
For More Information On This Product,
T SETUP
MC68360 USER’S MANUAL
TPAR 1
Go to: www.freescale.com
T WIDTH
T HOLD
TPAR 2

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