MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 365

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

determined by the ECO bit in the CMR. The DACKx timing is similar to the timing of the AS
pin. Thus, DACKx is the acknowledgment of the original burst request given on the DREQx
pin.
During each access to the device (i.e., DACKx is asserted), the IDMA will sample DREQx
at the S3 falling edge of the bus cycle to determine whether the burst should continue. If
DREQx is asserted, the burst continues. If DREQx is negated, the burst ceases, and another
operand transfer to/from the device does not occur until DREQx is asserted again. If DREQx
is negated, but not in time to stop the burst on this bus cycle, one additional bus cycle to the
device will occur before the IDMA stops the burst.
The previous paragraphs discuss the general rules; however, important special cases are
discussed in the following points:
1. The sample point at the S3 falling edge means the last S3 before the S4 edge that
2. The sample point at S3 assumes that the required setup time is met, as defined in Sec-
3. If SRM is cleared in the CMR (default condition), then DREQx is synchronized inter-
4. If operand packing is performed, the user does not need to negate DREQx on any par-
5. If operand packing is performed and the peripheral is the source and DREQx is negat-
6. If the access to the device is a fast termination access, the DREQx negation timing
completes the cycle. Thus, if wait states are inserted in the bus cycle, the sample point
is later in the cycle.
tion 10 Electrical Characteristics.
nally before it is used; therefore, DREQx must be negated one clock earlier than the
S3 falling edge to be recognized on that cycle.
ticular access to the device. For instance, if the source is a 32-bit memory and the des-
tination is an 8-bit peripheral, DREQx can be negated on the first, second, third, or
fourth byte access to the peripheral. In each case, if the DREQx negation timings are
met, the IDMA will stop accessing the peripheral immediately with no additional bus
cycles to the peripheral. Accesses to the peripheral will resume when DREQx is as-
serted.
ed to stop the burst, the IDMA will attempt to empty the contents of the DHR (by per-
forming one additional write cycle to memory) before giving up the bus. The IDMA
attempts to minimize the contents of the DHR between burst requests.
cannot be met, and one additional bus cycle will always occur to the device before the
burst stops.
Because DACKx timing is similar to AS timing, the user typically
uses the assertion of DACKx as an indication that DREQx is ne-
later than DSACKx because DSACKx pins are also sampled at
falling S3 to determine the end of the bus cycle.
gated.
To meet the S3 sampling time, DREQx should be negated no
Freescale Semiconductor, Inc.
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MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
IDMA Channels