MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 495

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.10.17.2 HDLC CHANNEL FRAME TRANSMISSION PROCESSING. The HDLC trans-
mitter is designed to work with almost no intervention from the CPU32+ core. When the
CPU32+ core enables one of the transmitters, it will start transmitting flags or idles as pro-
grammed in the HDLC mode register. The HDLC controller will poll the first BD in the trans-
mit channel’s BD table. When there is a frame to transmit, the HDLC controller will fetch the
data from memory and start transmitting the frame (after first transmitting the user-specified
minimum number of flags between frames). When the end of the current BD has been
reached and the last buffer in the frame bit is set, the CRC, if selected, and the closing flag
are appended. In HDLC, the LSB of each octet is transmitted first, and the MSB of the CRC
is transmitted first. A typical HDLC frame is shown in Figure 7-50.
Following the transmission of the closing flag, the HDLC controller writes the frame status
bits into the BD and clears the R-bit. When the end of the current BD has been reached and
the last bit is not set (working in multibuffer mode), only the R-bit is cleared. In either mode,
an interrupt may be issued if the I-bit in the Tx BD is set. The HDLC controller will then pro-
ceed to the next Tx BD in the table. In this way, the user may be interrupted after each buffer,
after a specific buffer has been transmitted, or after each frame.
To rearrange the transmit queue before the CP has completed transmission of all buffers,
issue the STOP TRANSMIT command. This technique can be useful for transmitting expe-
dited data before previously linked buffers or for error situations. When receiving the STOP
TRANSMIT command, the HDLC controller will abort the current frame being transmitted
and start transmitting idles or flags. When the HDLC controller is given the RESTART
TRANSMIT command, it resumes transmission.
To insert a high-priority frame without aborting the current frame, the GRACEFUL STOP
TRANSMIT command may be issued. A special interrupt (GRA) can be generated in the
event register when the current frame is complete.
OPENING FLAG
• May Be Used with the SCC DPLL
• Four Address Comparison Registers with Mask
• Maintenance of Five 16-Bit Error Counters
• Flag/Abort/Idle Generation/Detection
• Zero Insertion/Deletion
• 16-Bit or 32-Bit CRC-CCITT Generation/Checking
• Detection of Nonoctet Aligned Frames
• Detection of Frames That Are Too Long
• Programmable Flags (0–15) Between Successive Frames
• Automatic Retransmission in Case of Collision
8 BITS
ADDRESS
16 BITS
Freescale Semiconductor, Inc.
Figure 7-50. HDLC Framing Structure;
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
CONTROL
8 BITS
INFORMATION
(OPTIONAL)
8N BITS
Serial Communication Controllers (SCCs)
16 BITS
CRC
CLOSING FLAG
8 BITS