MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 747

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The SCM register is implemented using the general SCC mode register (GSMR) and the
protocol-specific mode register (PSMR). One GSMR and one PSMR exist for each SCC.
The definition of the PSMR differs based on the protocol used.
The UART mode register is now implemented using the GSMR and the PSMR. One GSMR
and one PSMR exist for each SCC. The definition of the PSMR differs based on the protocol
used.
QUICC serial interface clock route register (SICR). Note that many more options are now
available.
The TCS bit is implemented in the bank of clocks control in the three TxCS bits of the
QUICC SICR. Note that many more options are now available.
The EXTC bit becomes the EXTC1–EXTC0 bits in the BRGC. Note that more options are
now available. For compatibility, if the EXTC bit was cleared, then the EXTC1–EXTC0 bits
should also be cleared.
The WOMS bit gives the MC68302 wired-OR capability on the serial transmit data pin.
This can now be implemented (as well as other wired-OR capability) in the QUICC PxO-
DR registers, which can configure a pin to operate as wired-OR, regardless of whether it
is connected to the SCC.
The two MODE bits have been expanded to four MODE bits in the GSMR to include the
new protocols that the QUICC provides.
The ENT bit still exists, but is shifted two bit positions left in the GSMR.
The ENR bit still exists, but is shifted two bit positions left in the GSMR.
The DIAG bits still exist on the QUICC but are shifted left two positions. Normal operation
= 00, loopback = 01, and automatic echo = 10 still exist on the QUICC. Software operation
= 11 is now implemented by programming the PCPAR, PCDIR, PCODR, and PCINT in
the port C parallel I/O section. The new structure for software operation is much more flex-
ible than on the MC68302 and provides hardware-updated, accurate, real-time status.
Since the software operation combination is not needed in the QUICC DIAG bits in the
GSMR, this combination is used to support a new feature, simultaneous loopback and
echo.
The rest of the SCM bits differ based on protocol and are discussed in the following para-
graphs by protocol.
The SL bit is located in the PSMR.
The RTSM bit is located in the GSMR.
The CL bit becomes two bits in the PSMR for more character length options.
The FRZ bit is located in the PSMR.
The UM bits are located in the PSMR. Note that the 10 combination for asynchronous
DDCMP is now reserved.
The PEN bit is located in the PSMR.
The one RPM bit becomes two RPM bits in the PSMR for more receive parity options.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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