MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 628

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Management Controllers (SMCs)
7.11.12 SMC Transparent TSA Example
The following list is an initialization sequence for operation of the SMC1 transparent channel
over the TSA. It is assumed that the TSA and the TDM pins already have been set up to
route time slot data to the SMC transmitter and receiver. (7.8 Serial Interface with Time Slot
Assigner shows examples of how to configure the TSA.) The transmit and receive clocks
and synchronization signals are provided internally from the TSA.
7-304
10. Initialize the Tx BD. Assume the Tx data buffer is at $00002000 in main memory
11. Write $FF to the SMCE to clear any previous events.
12. Write $13 to the SMCM to enable all possible SMC interrupts.
13. Write $00000010 to the CIMR to allow SMC1 to generate a system interrupt. (The
14. Write $3830 to SMCMR to configure 8-bit characters, non-reversed data, and
15. Write $3833 to SMCMR to enable the SMC transmitter and receiver. This additional
1. Write RBASE and TBASE in the SMC parameter RAM to point to the Rx BD and Tx
2. Program the CR to execute the INIT RX & TX PARAMS command for this channel."
3. Write RFCR with $18 and TFCR with $18 for normal operation.
4. Write MRBLR with the maximum number of bytes per receive buffer. For this
5. Initialize the Rx BD. Assume the Rx data buffer is at $00001000 in main memory.
6. Initialize the Tx BD. Assume the Tx data buffer is at $00002000 in main memory and
Write $B000 to Rx_BD_Status. Write $0000 to Rx_BD_Length (not required—done
for instructional purposes only). Write $00001000 to Rx_BD_Pointer.
and contains five 8-bit characters. Write $B000 to Tx_BD_Status. Write $0005 to
Tx_BD_Length. Write $00002000 to Tx_BD_Pointer.
CICR should also be initialized.)
normal operation (not loopback). Notice that the transmitter and receiver have not
been enabled yet.
write ensures that the TEN and REN bits will be enabled last.
BD in the dual-port RAM. Assuming one Rx BD at the beginning of dual-port RAM
and one Tx BD following that Rx BD, write RBASE with $0000 and TBASE with
$0008.
For instance, to execute this command for SCC1, write $0001 to the CR. This com-
mand causes the RBPTR and TBPTR parameters of the serial channel to be updated
with the new values just programmed into RBASE and TBASE.
case,assume 16 bytes, so MRBLR = $0010.
Write $B000 to Rx_BD_Status. Write $0000 to Rx_BD_Length (not required—done
for instructional purposes only). Write $00001000 to Rx_BD_Pointer.
After 5 bytes have been transmitted, the Tx BD is closed. Addi-
tionally, the receive buffer is closed after 16 bytes have been re-
ceived. Any additional receive data beyond 16 bytes will cause
a busy (out-of-buffers) condition since only one Rx BD was pre-
pared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE