MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 250

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM60)
the bus. (The IDMA and SDMA have the ability to configure their bus arbitration level as
described in Section 7 Communication Processor Module (CPM)).
6.3.1.1 SIM60 INTERRUPT GENERATION. An overview of the QUICC interrupt structure
is shown in Figure 6-3. The lower half of the figure shows the SIM60. The SIM60 receives
interrupts from internal sources, such as the SWT and PIT, and external sources, such as
the IRQ7–IRQ1 lines.
If it generates an interrupt, the SWT always uses level 7; the PIT may use any level. The
IRQx pins choose the interrupt level associated with the pin (i.e., IRQ1 generates a level 1
interrupt, etc.). In addition, the CPM block may choose any level (1–7) for its interrupts.
The IMB architecture allows multiple interrupt sources to safely exist at the same level, a
process called interrupt arbitration. Once an interrupt acknowledge cycle occurs at the inter-
rupt level that matches a pending interrupt request, interrupt arbitration begins on the IMB.
The interrupt arbitration process is designed to choose between multiple requests at the
same level. For instance, if the PIT request is at level 4 but the CPM simultaneously is
requesting an interrupt at level 4, an interrupt arbitration process is required to decide who
wins the interrupt. (The interrupt arbitration process does not affect users who assign all
interrupt sources in the system to a unique interrupt level (1–7)).
6-6
Figure 6-2. System Configuration and Protection Logic
CLOCK
Freescale Semiconductor, Inc.
For More Information On This Product,
PRESCALER
2
9
MC68360 USER’S MANUAL
INTERRUPT MONITOR
Go to: www.freescale.com
CONFIGURATION
FAULT MONITOR
DOUBLE BUS
SPURIOUS
MONITOR
MODULE
STATUS
RESET
BUS
INTERRUPT TIMER
WATCHDOG
SOFTWARE
PERIODIC
INTERNAL BERR
IS SIGNALED
SYSTEM RESET
OR LEVEL 7
INTERRUPT
SYSTEM RESET
LEVEL 1 TO 7
INTERRUPT