MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 325

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SECTION 7
COMMUNICATION PROCESSOR MODULE (CPM)
INTRODUCTION
The CPM includes many blocks that work together to allow an extremely flexible and inte-
grated approach to solving many communications problems. The CPM (see Figure 7-1) in-
cludes the following modules:
• RISC Controller
• Four Full-Duplex Serial Communication Controllers (SCCs) Support the Following Pro-
• Four Independent Baud Rate Generators
• Two Serial Management Controllers (SMCs) Provide Additional UART and Totally
• Serial Interface Provides Nonmultiplexed Serial Interface (NMSI) for the Four SCCs (in-
• Time Slot Assigner (TSA) Supports Multiplexing of Data from any of the Four SCCs and
tocols:
—IEEE 802.3/Ethernet (Optional Feature on SCC)
—High-Level/Synchronous Data Link Control (HDLC/SDLC)
—HDLC Bus (Multidrop Bus Configuration of HDLC)
—AppleTalk (HDLC-Based Local Area Network (LAN) Protocol)
—Universal Asynchronous Receiver Transmitter (UART)
—Synchronous UART (Isochronous, 1x Clock Mode)
—Binary Synchronous Communication (BISYNC)
—Totally Transparent Operation
—Signaling System #7 (HDLC-Based Protocol. RAM Microcode Option Only)
— Profibus (RAM Microcode Option Only)
—Asynchronous HDLC (RAM Microcode Option Only)
—Multiple Chanel GCI (RAM Microcode Option Only)
—ATM Framing (RAM Microcode Option Only)
—Enhanced Ethernet Filtering (RAM Microcode Option Only)
Transparent Functionality or Support the GCI Channel 0 and 1 Monitor and C/I Chan-
nels in Integrated Services Digital Network (ISDN)
cludes TXD, RXD, TCLK, RCLK, RTS, CTS, and CD pins)
Two SMCs onto Two Time-Division Multiplexed (TDM) Interfaces. The TSA Supports
the Following TDM Formats:
—T1/CEPT Lines
—Pulse Code Modulation (PCM) Highway Interface
—ISDN Primary Rate
—Motorola Interchip Digital Link (IDL)
—General Circuit Interface (GCI), also known as IOM-2
—User-Defined Interfaces
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com