MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 620

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Management Controllers (SMCs)
Once the REN bit is set in SMCMR, the first time slot after frame sync causes the SMC
receiver to achieve synchronization. Data will begin to be received immediately, but only
during the defined receive time slots. The receiver will continue to receive data during its
defined time slots until the REN bit is cleared by the user. If the ENTER HUNT MODE com-
mand is executed, the receiver will lose synchronization, close the current buffer, and re-
synchronize to the first time slot after the frame sync.
Once the TEN bit is set in SMCMR, the SMC waits for the transmit FIFO to be loaded, before
attempting to achieve synchronization. Once the transmit FIFO is loaded, synchronization
and transmission begin on the first bit of the first time slot after the frame sync. Idles (ones)
are transmitted until data begins transmission.
If the SMC runs out of transmit buffers and a new transmit buffer is provided later, idles will
be transmitted during the gap between data buffers, and data transmission from the later
data buffer will begin at the beginning of an SMC time slot, but not necessarily the first time
slot after the frame sync. Thus, if the user wishes to maintain a certain bit alignment begin-
ning with the first time slot, the user should always make sure that at least one Tx BD is
always ready and that no underruns occur. Otherwise, the SMC transmitter should be dis-
abled and reenabled. See 7.11.5 Disabling the SMCs on the Fly for a description of how to
7-296
TDM Rx CLOCK
TDM Tx CLOCK
TDM Rx SYNC
TDM Tx SYNC
TDM Rx
TDM Tx
AFTER TEN IS SET,
TRANSMISSION
BEGINS HERE
Figure 7-79. Synchronization with the TSA
Freescale Semiconductor, Inc.
SMC1
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
IF SMC RUNS OUT OF TX BUFFERS AND NEW
ONES ARE PROVIDED LATER, TRANSMISSION
BEGINS AT THE BEGINNING OF EITHER TIME
SLOT
OR AFTER ENTER HUNT
AFTER REN IS SET
MODE COMMAND,
BEGINS HERE
RECEPTION
SMC1
SMC1
SMC1