MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 378

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

IDMA Channels
The user can terminate the transfer by setting the RST bit in the CMR and then issuing the
INIT_IDMA command.
The user can terminate the transfer with an "out of buffers" error if the V-bit of one of the BDs
is cleared by the user. When the RISC reaches this IDMA BD, it will terminate activity. This
technique is useful when the IDMA is required to stop transfers after fully completing a BD
transfer.
If the BCR is decremented to zero, the transfer from this BD completes, but the RISC con-
troller reloads the IDMA registers with the values from the next IDMA BD, and the IDMA
transfer continues. Thus, the fact that the BCR is decremented to zero does not terminate a
transfer in auto buffer mode; it only terminates the current BD transfer.
If DONEx is asserted externally, the transmission from this BD is terminated and the follow-
ing actions are performed by the RISC controller:
Thus the current buffer is closed immediately and all IDMA operation ceases.
7.6.4.8.3 Buffer Chaining Mode Termination. The user can suspend a transfer in auto
buffer mode by clearing the STR bit in the CMR. When STR is set once again, the transfer
will continue.
The user can terminate the transfer by setting the RST bit in the CMR and then issuing the
INIT_IDMA command.
The user can also terminate the transfer by setting the L-bit in the IDMA BD. When process-
ing of this BD has completed, the transmission will terminate with the DONE bit being set in
the CSR. This can cause an interrupt if the corresponding bit in the CMAR is set.
If the BCR is decremented to zero, the transfer from this BD completes, but the RISC con-
troller reloads the IDMA registers with the values from the next IDMA BD, and the IDMA
transfer continues. Thus, the fact that the BCR is decremented to zero does not terminate a
transfer in buffer chaining mode; it only terminates the current BD transfer.
If DONEx is asserted externally, the transmission from this BD is terminated and the follow-
ing actions are performed by the RISC controller.
7-54
1. Sets the Done Bit in the status register
2. Sets the DA bit in the BD
3. Clears the Valid bit in the BD
4. Resets the start bit in the CMR
1. Sets the Done Bit in the status register
2. Sets the Abort bit in the BD
3. Clears the Ready bit in the BD
4. Resets the start bit in the CMR
5. Sets the Reset bit in the CMR
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com